Microchip Technology Inc. ATSAMG51N18A 2024.06.03 ATSAMG51N18A false ADC Analog-to-Digital Converter ADC 0x0 0x0 0x50 registers n ADC 29 CDR0 Channel Data Register 0 0x50 32 read-only n 0x0 0x0 DATA Converted Data 0 12 read-only CDR1 Channel Data Register 0 0x54 32 read-only n 0x0 0x0 DATA Converted Data 0 12 read-only CDR2 Channel Data Register 0 0x58 32 read-only n 0x0 0x0 DATA Converted Data 0 12 read-only CDR3 Channel Data Register 0 0x5C 32 read-only n 0x0 0x0 DATA Converted Data 0 12 read-only CDR4 Channel Data Register 0 0x60 32 read-only n 0x0 0x0 DATA Converted Data 0 12 read-only CDR5 Channel Data Register 0 0x64 32 read-only n 0x0 0x0 DATA Converted Data 0 12 read-only CDR6 Channel Data Register 0 0x68 32 read-only n 0x0 0x0 DATA Converted Data 0 12 read-only CDR7 Channel Data Register 0 0x6C 32 read-only n 0x0 0x0 DATA Converted Data 0 12 read-only CDR[0] Channel Data Register 0xA0 32 read-only n 0x0 0x0 DATA Converted Data 0 12 read-only CDR[1] Channel Data Register 0xF4 32 read-only n 0x0 0x0 DATA Converted Data 0 12 read-only CDR[2] Channel Data Register 0x14C 32 read-only n 0x0 0x0 DATA Converted Data 0 12 read-only CDR[3] Channel Data Register 0x1A8 32 read-only n 0x0 0x0 DATA Converted Data 0 12 read-only CDR[4] Channel Data Register 0x208 32 read-only n 0x0 0x0 DATA Converted Data 0 12 read-only CDR[5] Channel Data Register 0x26C 32 read-only n 0x0 0x0 DATA Converted Data 0 12 read-only CDR[6] Channel Data Register 0x2D4 32 read-only n 0x0 0x0 DATA Converted Data 0 12 read-only CDR[7] Channel Data Register 0x340 32 read-only n 0x0 0x0 DATA Converted Data 0 12 read-only CHDR Channel Disable Register 0x14 32 write-only n 0x0 0x0 CH0 Channel 0 Disable 0 1 write-only CH1 Channel 1 Disable 1 1 write-only CH2 Channel 2 Disable 2 1 write-only CH3 Channel 3 Disable 3 1 write-only CH4 Channel 4 Disable 4 1 write-only CH5 Channel 5 Disable 5 1 write-only CH6 Channel 6 Disable 6 1 write-only CH7 Channel 7 Disable 7 1 write-only CHER Channel Enable Register 0x10 32 write-only n 0x0 0x0 CH0 Channel 0 Enable 0 1 write-only CH1 Channel 1 Enable 1 1 write-only CH2 Channel 2 Enable 2 1 write-only CH3 Channel 3 Enable 3 1 write-only CH4 Channel 4 Enable 4 1 write-only CH5 Channel 5 Enable 5 1 write-only CH6 Channel 6 Enable 6 1 write-only CH7 Channel 7 Enable 7 1 write-only CHSR Channel Status Register 0x18 32 read-only n 0x0 0x0 CH0 Channel 0 Status 0 1 read-only CH1 Channel 1 Status 1 1 read-only CH2 Channel 2 Status 2 1 read-only CH3 Channel 3 Status 3 1 read-only CH4 Channel 4 Status 4 1 read-only CH5 Channel 5 Status 5 1 read-only CH6 Channel 6 Status 6 1 read-only CH7 Channel 7 Status 7 1 read-only CR Control Register 0x0 32 write-only n 0x0 0x0 AUTOCAL Automatic Calibration of ADC 3 1 write-only START Start Conversion 1 1 write-only SWRST Software Reset 0 1 write-only CWR Compare Window Register 0x44 32 read-write n 0x0 0x0 HIGHTHRES High Threshold 16 12 read-write LOWTHRES Low Threshold 0 12 read-write EMR Extended Mode Register 0x40 32 read-write n 0x0 0x0 ASTE Averaging on Single Trigger Event 20 1 read-write MULTI_TRIG_AVERAGE The average requests several trigger events. 0 SINGLE_TRIG_AVERAGE The average requests only one trigger event. 1 CMPALL Compare All Channels 9 1 read-write CMPFILTER Compare Event Filtering 12 2 read-write CMPMODE Comparison Mode 0 2 read-write LOW Generates an event when the converted data is lower than the low threshold of the window. 0x0 HIGH Generates an event when the converted data is higher than the high threshold of the window. 0x1 IN Generates an event when the converted data is in the comparison window. 0x2 OUT Generates an event when the converted data is out of the comparison window. 0x3 CMPSEL Comparison Selected Channel 4 4 read-write OSR Over Sampling Rate 16 2 read-write NO_AVERAGE no averaging. ADC sample rate is maximum. 0x0 OSR4 1-bit enhanced resolution by averaging. ADC sample rate divided by 4. 0x1 OSR16 2-bit enhanced resolution by averaging. ADC sample rate divided by 16. 0x2 TAG Tag of the ADC_LDCR 24 1 read-write IDR Interrupt Disable Register 0x28 32 write-only n 0x0 0x0 COMPE Comparison Event Interrupt Disable 26 1 write-only DRDY Data Ready Interrupt Disable 24 1 write-only ENDRX End of Receive Buffer Interrupt Disable 27 1 write-only EOC0 End of Conversion Interrupt Disable 0 0 1 write-only EOC1 End of Conversion Interrupt Disable 1 1 1 write-only EOC2 End of Conversion Interrupt Disable 2 2 1 write-only EOC3 End of Conversion Interrupt Disable 3 3 1 write-only EOC4 End of Conversion Interrupt Disable 4 4 1 write-only EOC5 End of Conversion Interrupt Disable 5 5 1 write-only EOC6 End of Conversion Interrupt Disable 6 6 1 write-only EOC7 End of Conversion Interrupt Disable 7 7 1 write-only EOCAL End of Calibration Sequence 23 1 write-only GOVRE General Overrun Error Interrupt Disable 25 1 write-only LCCHG Last Channel Change Interrupt Disable 19 1 write-only RXBUFF Receive Buffer Full Interrupt Disable 28 1 write-only IER Interrupt Enable Register 0x24 32 write-only n 0x0 0x0 COMPE Comparison Event Interrupt Enable 26 1 write-only DRDY Data Ready Interrupt Enable 24 1 write-only ENDRX End of Receive Buffer Interrupt Enable 27 1 write-only EOC0 End of Conversion Interrupt Enable 0 0 1 write-only EOC1 End of Conversion Interrupt Enable 1 1 1 write-only EOC2 End of Conversion Interrupt Enable 2 2 1 write-only EOC3 End of Conversion Interrupt Enable 3 3 1 write-only EOC4 End of Conversion Interrupt Enable 4 4 1 write-only EOC5 End of Conversion Interrupt Enable 5 5 1 write-only EOC6 End of Conversion Interrupt Enable 6 6 1 write-only EOC7 End of Conversion Interrupt Enable 7 7 1 write-only EOCAL End of Calibration Sequence 23 1 write-only GOVRE General Overrun Error Interrupt Enable 25 1 write-only LCCHG Last Channel Change Interrupt Enable 19 1 write-only RXBUFF Receive Buffer Full Interrupt Enable 28 1 write-only IMR Interrupt Mask Register 0x2C 32 read-only n 0x0 0x0 COMPE Comparison Event Interrupt Mask 26 1 read-only DRDY Data Ready Interrupt Mask 24 1 read-only ENDRX End of Receive Buffer Interrupt Mask 27 1 read-only EOC0 End of Conversion Interrupt Mask 0 0 1 read-only EOC1 End of Conversion Interrupt Mask 1 1 1 read-only EOC2 End of Conversion Interrupt Mask 2 2 1 read-only EOC3 End of Conversion Interrupt Mask 3 3 1 read-only EOC4 End of Conversion Interrupt Mask 4 4 1 read-only EOC5 End of Conversion Interrupt Mask 5 5 1 read-only EOC6 End of Conversion Interrupt Mask 6 6 1 read-only EOC7 End of Conversion Interrupt Mask 7 7 1 read-only EOCAL End of Calibration Sequence 23 1 read-only GOVRE General Overrun Error Interrupt Mask 25 1 read-only LCCHG Last Channel Change Interrupt Mask 19 1 read-only RXBUFF Receive Buffer Full Interrupt Mask 28 1 read-only ISR Interrupt Status Register 0x30 32 read-only n 0x0 0x0 COMPE Comparison Error 26 1 read-only DRDY Data Ready 24 1 read-only ENDRX End of Receiver Transfer 27 1 read-only EOC0 End of Conversion 0 0 1 read-only EOC1 End of Conversion 1 1 1 read-only EOC2 End of Conversion 2 2 1 read-only EOC3 End of Conversion 3 3 1 read-only EOC4 End of Conversion 4 4 1 read-only EOC5 End of Conversion 5 5 1 read-only EOC6 End of Conversion 6 6 1 read-only EOC7 End of Conversion 7 7 1 read-only EOCAL End of Calibration Sequence 23 1 read-only GOVRE General Overrun Error 25 1 read-only LCCHG Last Channel Change 19 1 read-only RXBUFF Reception Buffer Full 28 1 read-only LCCWR Last Channel Compare Window Register 0x38 32 read-write n 0x0 0x0 HIGHTHRES High Threshold 16 12 read-write LOWTHRES Low Threshold 0 12 read-write LCDR Last Converted Data Register 0x20 32 read-only n 0x0 0x0 CHNB Channel Number 12 4 read-only LDATA Last Data Converted 0 12 read-only LCTMR Last Channel Trigger Mode Register 0x34 32 read-write n 0x0 0x0 CMPMOD Last Channel Comparison Mode 4 2 read-write LOW Generates an event when the converted data is lower than the low threshold of the window. 0x0 HIGH Generates an event when the converted data is higher than the high threshold of the window. 0x1 IN Generates an event when the converted data is in the comparison window. 0x2 OUT Generates an event when the converted data is out of the comparison window. 0x3 DUALTRIG Dual Trigger ON 0 1 read-write MR Mode Register 0x4 32 read-write n 0x0 0x0 DIV1 ADCClock Prescaler Division forced to 1 22 1 read-write NO_DIV1 The PRESCAL field is used to generate the ADCClock unless DIV3 is written to 1. 0 FORCE_DIV1 The ADCClock equals MCK (PRESCAL and DIV3 fields have no effects). 1 DIV3 ADCClock Prescaler Division forced to 3 30 1 read-write NO_DIV3 The PRESCAL field is used to generate the ADCClock unless DIV1 is written to 1. 0 FORCE_DIV3 The ADCClock equals MCK/3 unless DIV1 is written to 1. 1 FREERUN Free Run Mode 7 1 read-write OFF Normal Mode 0 ON Free Run Mode: Never wait for any trigger. 1 LOWRES Resolution 4 1 read-write BITS_12 12-bit resolution. For higher resolution by averaging, please refer to "ADC Extended Mode Register" on page 81 0 BITS_10 10-bit resolution 1 PRESCAL Prescaler Rate Selection 8 8 read-write SLEEP Sleep Mode 5 1 read-write NORMAL Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions 0 SLEEP Sleep Mode: The ADC Core and reference voltage circuitry are OFF between conversions 1 STARTUP Start Up Time 16 4 read-write SUT0 0 periods of ADCClock 0x0 SUT8 8 periods of ADCClock 0x1 SUT16 16 periods of ADCClock 0x2 SUT24 24 periods of ADCClock 0x3 SUT64 64 periods of ADCClock 0x4 SUT80 80 periods of ADCClock 0x5 SUT96 96 periods of ADCClock 0x6 SUT112 112 periods of ADCClock 0x7 SUT512 512 periods of ADCClock 0x8 SUT576 576 periods of ADCClock 0x9 SUT640 640 periods of ADCClock 0xA SUT704 704 periods of ADCClock 0xB SUT768 768 periods of ADCClock 0xC SUT832 832 periods of ADCClock 0xD SUT896 896 periods of ADCClock 0xE SUT960 960 periods of ADCClock 0xF TRACKTIM Tracking Time 24 4 read-write TRANSFER Transfer Period 28 2 read-write TRGEN Trigger Enable 0 1 read-write DIS Hardware triggers are disabled. Starting a conversion is only possible by software. 0 EN Hardware trigger selected by TRGSEL field is enabled. 1 TRGSEL Trigger Selection 1 3 read-write ADC_TRIG0 External trigger 0x0 ADC_TRIG1 TIO Output of the Timer Counter Channel 0 0x1 ADC_TRIG2 TIO Output of the Timer Counter Channel 1 0x2 ADC_TRIG3 TIO Output of the Timer Counter Channel 2 0x3 ADC_TRIG4 RTCOUT0 0x4 ADC_TRIG5 RTTINC 0x5 USEQ Use Sequence Enable 31 1 read-write NUM_ORDER Normal Mode: The controller converts channels in a simple numeric order depending only on the channel index. 0 REG_ORDER User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 register and can be used to convert several times the same channel. 1 OVER Overrun Status Register 0x3C 32 read-only n 0x0 0x0 OVRE0 Overrun Error 0 0 1 read-only OVRE1 Overrun Error 1 1 1 read-only OVRE2 Overrun Error 2 2 1 read-only OVRE3 Overrun Error 3 3 1 read-only OVRE4 Overrun Error 4 4 1 read-only OVRE5 Overrun Error 5 5 1 read-only OVRE6 Overrun Error 6 6 1 read-only OVRE7 Overrun Error 7 7 1 read-only PTCR Transfer Control Register 0x120 32 write-only n 0x0 0x0 RXTDIS Receiver Transfer Disable 1 1 write-only RXTEN Receiver Transfer Enable 0 1 write-only TXTDIS Transmitter Transfer Disable 9 1 write-only TXTEN Transmitter Transfer Enable 8 1 write-only PTSR Transfer Status Register 0x124 32 read-only n 0x0 0x0 RXTEN Receiver Transfer Enable 0 1 read-only TXTEN Transmitter Transfer Enable 8 1 read-only RCR Receive Counter Register 0x104 32 read-write n 0x0 0x0 RXCTR Receive Counter Register 0 16 read-write RNCR Receive Next Counter Register 0x114 32 read-write n 0x0 0x0 RXNCTR Receive Next Counter 0 16 read-write RNPR Receive Next Pointer Register 0x110 32 read-write n 0x0 0x0 RXNPTR Receive Next Pointer 0 32 read-write RPR Receive Pointer Register 0x100 32 read-write n 0x0 0x0 RXPTR Receive Pointer Register 0 32 read-write SEQR1 Channel Sequence Register 1 0x8 32 read-write n 0x0 0x0 USCH1 User Sequence Number 1 0 4 read-write USCH2 User Sequence Number 2 4 4 read-write USCH3 User Sequence Number 3 8 4 read-write USCH4 User Sequence Number 4 12 4 read-write USCH5 User Sequence Number 5 16 4 read-write USCH6 User Sequence Number 6 20 4 read-write USCH7 User Sequence Number 7 24 4 read-write WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 0x414443 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only CHIPID Chip Identifier CHIPID 0x0 0x0 0x200 registers n 0x0 0x8 registers n CIDR Chip ID Register 0x0 32 read-only n 0x0 0x0 ARCH Architecture Identifier 20 8 read-only SAMG51 SAMG51 (WLCSP package) 0x43 EPROC Embedded Processor 5 3 read-only ARM946ES ARM946ES 0x1 ARM7TDMI ARM7TDMI 0x2 CM3 Cortex-M3 0x3 ARM920T ARM920T 0x4 ARM926EJS ARM926EJS 0x5 CA5 Cortex-A5 0x6 CM4 Cortex-M4 0x7 EXT Extension Flag 31 1 read-only NVPSIZ Nonvolatile Program Memory Size 8 4 read-only NONE None 0x0 8K 8 Kbytes 0x1 16K 16 Kbytes 0x2 32K 32 Kbytes 0x3 64K 64 Kbytes 0x5 128K 128 Kbytes 0x7 256K 256 Kbytes 0x9 512K 512 Kbytes 0xA 1024K 1024 Kbytes 0xC 2048K 2048 Kbytes 0xE NVPSIZ2 Second Nonvolatile Program Memory Size 12 4 read-only NONE None 0x0 8K 8 Kbytes 0x1 16K 16 Kbytes 0x2 32K 32 Kbytes 0x3 64K 64 Kbytes 0x5 128K 128 Kbytes 0x7 256K 256 Kbytes 0x9 512K 512 Kbytes 0xA 1024K 1024 Kbytes 0xC 2048K 2048 Kbytes 0xE NVPTYP Nonvolatile Program Memory Type 28 3 read-only ROM ROM 0x0 ROMLESS ROMless or on-chip Flash 0x1 FLASH Embedded Flash Memory 0x2 ROM_FLASH ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size 0x3 SRAM SRAM emulating ROM 0x4 SRAMSIZ Internal SRAM Size 16 4 read-only 48K 48 Kbytes 0x0 192K 192 Kbytes 0x1 2K 2 Kbytes 0x2 6K 6 Kbytes 0x3 24K 24 Kbytes 0x4 4K 4 Kbytes 0x5 80K 80 Kbytes 0x6 160K 160 Kbytes 0x7 8K 8 Kbytes 0x8 16K 16 Kbytes 0x9 32K 32 Kbytes 0xA 64K 64 Kbytes 0xB 128K 128 Kbytes 0xC 256K 256 Kbytes 0xD 96K 96 Kbytes 0xE 512K 512 Kbytes 0xF VERSION Version of the Device 0 5 read-only EXID Chip ID Extension Register 0x4 32 read-only n 0x0 0x0 EXID Chip ID Extension 0 32 read-only EFC Embedded Flash Controller EFC 0x0 0x0 0x200 registers n 0x0 0x10 registers n EFC 6 EEFC_FCR EEFC Flash Command Register 0x4 32 write-only n 0x0 0x0 FARG Flash Command Argument 8 16 FCMD Flash Command 0 8 FCMDSelect GETD Get Flash descriptor 0x00 WP Write page 0x01 WPL Write page and lock 0x02 EWP Erase page and write page 0x03 EWPL Erase page and write page then lock 0x04 EA Erase all 0x05 EPA Erase pages 0x07 SLB Set lock bit 0x08 CLB Clear lock bit 0x09 GLB Get lock bit 0x0A SGPB Set GPNVM bit 0x0B CGPB Clear GPNVM bit 0x0C GGPB Get GPNVM bit 0x0D STUI Start read unique identifier 0x0E SPUI Stop read unique identifier 0x0F GCALB Get CALIB bit 0x10 ES Erase sector 0x11 WUS Write user signature 0x12 EUS Erase user signature 0x13 STUS Start read user signature 0x14 SPUS Stop read user signature 0x15 FKEY Flash Writing Protection Key 24 8 FKEYSelect PASSWD The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. 0x5A EEFC_FMR EEFC Flash Mode Register 0x0 32 read-write n 0x0 0x0 CLOE Code Loop Optimization Enable 26 1 FAM Flash Access Mode 24 1 FRDY Flash Ready Interrupt Enable 0 1 FWS Flash Wait State 8 4 SCOD Sequential Code Optimization Disable 16 1 EEFC_FRR EEFC Flash Result Register 0xC 32 read-only n 0x0 0x0 FVALUE Flash Result Value 0 32 EEFC_FSR EEFC Flash Status Register 0x8 32 read-only n 0x0 0x0 FCMDE Flash Command Error Status (cleared on read or by writing EEFC_FCR) 1 1 FLERR Flash Error Status (cleared when a programming operation starts) 3 1 FLOCKE Flash Lock Error Status (cleared on read) 2 1 FRDY Flash Ready Status (cleared when Flash is busy) 0 1 FCR EEFC Flash Command Register 0x4 32 write-only n 0x0 0x0 FARG Flash Command Argument 8 16 write-only FCMD Flash Command 0 8 write-only GETD Get Flash descriptor 0x00 WP Write page 0x01 WPL Write page and lock 0x02 EWP Erase page and write page 0x03 EWPL Erase page and write page then lock 0x04 EA Erase all 0x05 EPA Erase pages 0x07 SLB Set lock bit 0x08 CLB Clear lock bit 0x09 GLB Get lock bit 0x0A SGPB Set GPNVM bit 0x0B CGPB Clear GPNVM bit 0x0C GGPB Get GPNVM bit 0x0D STUI Start read unique identifier 0x0E SPUI Stop read unique identifier 0x0F GCALB Get CALIB bit 0x10 ES Erase sector 0x11 WUS Write user signature 0x12 EUS Erase user signature 0x13 STUS Start read user signature 0x14 SPUS Stop read user signature 0x15 FKEY Flash Writing Protection Key 24 8 write-only PASSWD The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. 0x5A FMR EEFC Flash Mode Register 0x0 32 read-write n 0x0 0x0 CLOE Code Loop Optimization Enable 26 1 read-write FAM Flash Access Mode 24 1 read-write FRDY Ready Interrupt Enable 0 1 read-write FWS Flash Wait State 8 4 read-write SCOD Sequential Code Optimization Disable 16 1 read-write FRR EEFC Flash Result Register 0xC 32 read-only n 0x0 0x0 FVALUE Flash Result Value 0 32 read-only FSR EEFC Flash Status Register 0x8 32 read-only n 0x0 0x0 FCMDE Flash Command Error Status 1 1 read-only FLERR Flash Error Status 3 1 read-only FLOCKE Flash Lock Error Status 2 1 read-only FRDY Flash Ready Status 0 1 read-only GPBR General Purpose Backup Registers SYSC 0x0 0x0 0x200 registers n GPBR0 General Purpose Backup Register 0x0 32 read-write n GPBR_VALUE Value of GPBR x 0 32 read-write GPBR1 General Purpose Backup Register 0x4 32 read-write n GPBR_VALUE Value of GPBR x 0 32 read-write GPBR2 General Purpose Backup Register 0x8 32 read-write n GPBR_VALUE Value of GPBR x 0 32 read-write GPBR3 General Purpose Backup Register 0xC 32 read-write n GPBR_VALUE Value of GPBR x 0 32 read-write GPBR4 General Purpose Backup Register 0x10 32 read-write n GPBR_VALUE Value of GPBR x 0 32 read-write GPBR5 General Purpose Backup Register 0x14 32 read-write n GPBR_VALUE Value of GPBR x 0 32 read-write GPBR6 General Purpose Backup Register 0x18 32 read-write n GPBR_VALUE Value of GPBR x 0 32 read-write GPBR7 General Purpose Backup Register 0x1C 32 read-write n GPBR_VALUE Value of GPBR x 0 32 read-write GPBR[0] General Purpose Backup Register 0x0 32 read-write n 0x0 0x0 GPBR_VALUE Value of GPBR x 0 32 read-write GPBR[1] General Purpose Backup Register 0x4 32 read-write n 0x0 0x0 GPBR_VALUE Value of GPBR x 0 32 read-write GPBR[2] General Purpose Backup Register 0xC 32 read-write n 0x0 0x0 GPBR_VALUE Value of GPBR x 0 32 read-write GPBR[3] General Purpose Backup Register 0x18 32 read-write n 0x0 0x0 GPBR_VALUE Value of GPBR x 0 32 read-write GPBR[4] General Purpose Backup Register 0x28 32 read-write n 0x0 0x0 GPBR_VALUE Value of GPBR x 0 32 read-write GPBR[5] General Purpose Backup Register 0x3C 32 read-write n 0x0 0x0 GPBR_VALUE Value of GPBR x 0 32 read-write GPBR[6] General Purpose Backup Register 0x54 32 read-write n 0x0 0x0 GPBR_VALUE Value of GPBR x 0 32 read-write GPBR[7] General Purpose Backup Register 0x70 32 read-write n 0x0 0x0 GPBR_VALUE Value of GPBR x 0 32 read-write MATRIX AHB Bus Matrix MATRIX 0x0 0x0 0x200 registers n CCFG_SYSIO System I/O Configuration Register 0x114 32 read-write n 0x0 0x0 SYSIO12 PB12 or ERASE Assignment 12 1 read-write SYSIO4 PB4 or TDI Assignment 4 1 read-write SYSIO5 PB5 or TDO/TRACESWO Assignment 5 1 read-write SYSIO6 PB6 or TMS/SWDIO Assignment 6 1 read-write SYSIO7 PB7 or TCK/SWCLK Assignment 7 1 read-write MCFG0 Master Configuration Register 0x0 32 read-write n ULBT Undefined Length Burst Type 0 3 read-write INFINITE No predicted end of burst is generated and therefore INCR bursts coming from this master cannot be broken. 0x0 SINGLE The undefined length burst is treated as a succession of single access allowing rearbitration at each beat of the INCR burst. 0x1 FOUR_BEAT The undefined length burst is split into a 4-beat bursts allowing rearbitration at each 4-beat burst end. 0x2 EIGHT_BEAT The undefined length burst is split into 8-beat bursts allowing rearbitration at each 8-beat burst end. 0x3 SIXTEEN_BEAT The undefined length burst is split into 16-beat bursts allowing rearbitration at each 16-beat burst end. 0x4 MCFG1 Master Configuration Register 0x4 32 read-write n ULBT Undefined Length Burst Type 0 3 read-write INFINITE No predicted end of burst is generated and therefore INCR bursts coming from this master cannot be broken. 0x0 SINGLE The undefined length burst is treated as a succession of single access allowing rearbitration at each beat of the INCR burst. 0x1 FOUR_BEAT The undefined length burst is split into a 4-beat bursts allowing rearbitration at each 4-beat burst end. 0x2 EIGHT_BEAT The undefined length burst is split into 8-beat bursts allowing rearbitration at each 8-beat burst end. 0x3 SIXTEEN_BEAT The undefined length burst is split into 16-beat bursts allowing rearbitration at each 16-beat burst end. 0x4 MCFG2 Master Configuration Register 0x8 32 read-write n ULBT Undefined Length Burst Type 0 3 read-write INFINITE No predicted end of burst is generated and therefore INCR bursts coming from this master cannot be broken. 0x0 SINGLE The undefined length burst is treated as a succession of single access allowing rearbitration at each beat of the INCR burst. 0x1 FOUR_BEAT The undefined length burst is split into a 4-beat bursts allowing rearbitration at each 4-beat burst end. 0x2 EIGHT_BEAT The undefined length burst is split into 8-beat bursts allowing rearbitration at each 8-beat burst end. 0x3 SIXTEEN_BEAT The undefined length burst is split into 16-beat bursts allowing rearbitration at each 16-beat burst end. 0x4 MCFG[0] Master Configuration Register 0x0 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 read-write INFINITE No predicted end of burst is generated and therefore INCR bursts coming from this master cannot be broken. 0x0 SINGLE The undefined length burst is treated as a succession of single access allowing rearbitration at each beat of the INCR burst. 0x1 FOUR_BEAT The undefined length burst is split into a 4-beat bursts allowing rearbitration at each 4-beat burst end. 0x2 EIGHT_BEAT The undefined length burst is split into 8-beat bursts allowing rearbitration at each 8-beat burst end. 0x3 SIXTEEN_BEAT The undefined length burst is split into 16-beat bursts allowing rearbitration at each 16-beat burst end. 0x4 MCFG[1] Master Configuration Register 0x4 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 read-write INFINITE No predicted end of burst is generated and therefore INCR bursts coming from this master cannot be broken. 0x0 SINGLE The undefined length burst is treated as a succession of single access allowing rearbitration at each beat of the INCR burst. 0x1 FOUR_BEAT The undefined length burst is split into a 4-beat bursts allowing rearbitration at each 4-beat burst end. 0x2 EIGHT_BEAT The undefined length burst is split into 8-beat bursts allowing rearbitration at each 8-beat burst end. 0x3 SIXTEEN_BEAT The undefined length burst is split into 16-beat bursts allowing rearbitration at each 16-beat burst end. 0x4 MCFG[2] Master Configuration Register 0xC 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 read-write INFINITE No predicted end of burst is generated and therefore INCR bursts coming from this master cannot be broken. 0x0 SINGLE The undefined length burst is treated as a succession of single access allowing rearbitration at each beat of the INCR burst. 0x1 FOUR_BEAT The undefined length burst is split into a 4-beat bursts allowing rearbitration at each 4-beat burst end. 0x2 EIGHT_BEAT The undefined length burst is split into 8-beat bursts allowing rearbitration at each 8-beat burst end. 0x3 SIXTEEN_BEAT The undefined length burst is split into 16-beat bursts allowing rearbitration at each 16-beat burst end. 0x4 PRAS0 Priority Register A for Slave 0 0x80 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write PRAS1 Priority Register A for Slave 1 0x88 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write PRAS2 Priority Register A for Slave 2 0x90 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write PRAS3 Priority Register A for Slave 3 0x98 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write SCFG0 Slave Configuration Register 0x40 32 read-write n ARBT Arbitration Type 24 2 read-write ROUND_ROBIN Round-robin arbitration 0 FIXED_PRIORITY Fixed priority arbitration 1 DEFMSTR_TYPE Default Master Type 16 2 read-write NO_DEFAULT At the end of current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in having a one cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST At the end of current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having the one cycle latency when the last master tries to access the slave again. 0x1 FIXED At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having the one cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 3 read-write SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 read-write SCFG1 Slave Configuration Register 0x44 32 read-write n ARBT Arbitration Type 24 2 read-write ROUND_ROBIN Round-robin arbitration 0 FIXED_PRIORITY Fixed priority arbitration 1 DEFMSTR_TYPE Default Master Type 16 2 read-write NO_DEFAULT At the end of current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in having a one cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST At the end of current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having the one cycle latency when the last master tries to access the slave again. 0x1 FIXED At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having the one cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 3 read-write SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 read-write SCFG2 Slave Configuration Register 0x48 32 read-write n ARBT Arbitration Type 24 2 read-write ROUND_ROBIN Round-robin arbitration 0 FIXED_PRIORITY Fixed priority arbitration 1 DEFMSTR_TYPE Default Master Type 16 2 read-write NO_DEFAULT At the end of current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in having a one cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST At the end of current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having the one cycle latency when the last master tries to access the slave again. 0x1 FIXED At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having the one cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 3 read-write SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 read-write SCFG3 Slave Configuration Register 0x4C 32 read-write n ARBT Arbitration Type 24 2 read-write ROUND_ROBIN Round-robin arbitration 0 FIXED_PRIORITY Fixed priority arbitration 1 DEFMSTR_TYPE Default Master Type 16 2 read-write NO_DEFAULT At the end of current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in having a one cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST At the end of current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having the one cycle latency when the last master tries to access the slave again. 0x1 FIXED At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having the one cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 3 read-write SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 read-write SCFG[0] Slave Configuration Register 0x80 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 2 read-write ROUND_ROBIN Round-robin arbitration 0 FIXED_PRIORITY Fixed priority arbitration 1 DEFMSTR_TYPE Default Master Type 16 2 read-write NO_DEFAULT At the end of current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in having a one cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST At the end of current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having the one cycle latency when the last master tries to access the slave again. 0x1 FIXED At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having the one cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 3 read-write SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 read-write SCFG[1] Slave Configuration Register 0xC4 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 2 read-write ROUND_ROBIN Round-robin arbitration 0 FIXED_PRIORITY Fixed priority arbitration 1 DEFMSTR_TYPE Default Master Type 16 2 read-write NO_DEFAULT At the end of current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in having a one cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST At the end of current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having the one cycle latency when the last master tries to access the slave again. 0x1 FIXED At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having the one cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 3 read-write SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 read-write SCFG[2] Slave Configuration Register 0x10C 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 2 read-write ROUND_ROBIN Round-robin arbitration 0 FIXED_PRIORITY Fixed priority arbitration 1 DEFMSTR_TYPE Default Master Type 16 2 read-write NO_DEFAULT At the end of current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in having a one cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST At the end of current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having the one cycle latency when the last master tries to access the slave again. 0x1 FIXED At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having the one cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 3 read-write SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 read-write SCFG[3] Slave Configuration Register 0x158 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 2 read-write ROUND_ROBIN Round-robin arbitration 0 FIXED_PRIORITY Fixed priority arbitration 1 DEFMSTR_TYPE Default Master Type 16 2 read-write NO_DEFAULT At the end of current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in having a one cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST At the end of current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having the one cycle latency when the last master tries to access the slave again. 0x1 FIXED At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having the one cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 3 read-write SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 read-write WPMR Write Protection Mode Register 0x1E4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 0x4D4154 WPSR Write Protection Status Register 0x1E8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only MEM2MEM Memory to Memory MEM2MEM 0x0 0x0 0x50 registers n MEM2MEM 15 IDR Memory to Memory Interrupt Disable Register 0xC 32 write-only n 0x0 0x0 RXBUFF Buffer Full Interrupt Disable 1 1 write-only RXEND End of Transfer Interrupt Disable 0 1 write-only IER Memory to Memory Interrupt Enable Register 0x8 32 write-only n 0x0 0x0 RXBUFF Buffer Full Interrupt Enable 1 1 write-only RXEND End of Transfer Interrupt Enable 0 1 write-only IMR Memory to Memory Interrupt Mask Register 0x10 32 read-only n 0x0 0x0 RXBUFF Buffer Full Interrupt Mask 1 1 read-only RXEND End of Transfer Interrupt Mask 0 1 read-only ISR Memory to Memory Interrupt Status Register 0x14 32 read-only n 0x0 0x0 RXBUFF Buffer Full 1 1 read-only RXEND End of Transfer 0 1 read-only MR Memory to Memory Mode Register 0x4 32 read-write n 0x0 0x0 TSIZE Transfer Size 0 2 read-write T_8BIT The buffer size is defined in byte. 0x0 T_16BIT The buffer size is defined in half-word (16-bit). 0x1 T_32BIT The buffer size is defined in word (32-bit). Default value. 0x2 PTCR Transfer Control Register 0x120 32 write-only n 0x0 0x0 RXTDIS Receiver Transfer Disable 1 1 write-only RXTEN Receiver Transfer Enable 0 1 write-only TXTDIS Transmitter Transfer Disable 9 1 write-only TXTEN Transmitter Transfer Enable 8 1 write-only PTSR Transfer Status Register 0x124 32 read-only n 0x0 0x0 RXTEN Receiver Transfer Enable 0 1 read-only TXTEN Transmitter Transfer Enable 8 1 read-only RCR Receive Counter Register 0x104 32 read-write n 0x0 0x0 RXCTR Receive Counter Register 0 16 read-write RNCR Receive Next Counter Register 0x114 32 read-write n 0x0 0x0 RXNCTR Receive Next Counter 0 16 read-write RNPR Receive Next Pointer Register 0x110 32 read-write n 0x0 0x0 RXNPTR Receive Next Pointer 0 32 read-write RPR Receive Pointer Register 0x100 32 read-write n 0x0 0x0 RXPTR Receive Pointer Register 0 32 read-write TCR Transmit Counter Register 0x10C 32 read-write n 0x0 0x0 TXCTR Transmit Counter Register 0 16 read-write THR Memory to Memory Transfer Holding Register 0x0 32 read-write n 0x0 0x0 THDATA Transfer Holding Data 0 32 read-write TNCR Transmit Next Counter Register 0x11C 32 read-write n 0x0 0x0 TXNCTR Transmit Counter Next 0 16 read-write TNPR Transmit Next Pointer Register 0x118 32 read-write n 0x0 0x0 TXNPTR Transmit Next Pointer 0 32 read-write TPR Transmit Pointer Register 0x108 32 read-write n 0x0 0x0 TXPTR Transmit Counter Register 0 32 read-write PIOA Parallel Input/Output Controller A PIO 0x0 0x0 0x200 registers n PIOA 11 ABCDSR0 Peripheral Select Register 0x70 32 read-write n P0 Peripheral Select 0 1 read-write P1 Peripheral Select 1 1 read-write P10 Peripheral Select 10 1 read-write P11 Peripheral Select 11 1 read-write P12 Peripheral Select 12 1 read-write P13 Peripheral Select 13 1 read-write P14 Peripheral Select 14 1 read-write P15 Peripheral Select 15 1 read-write P16 Peripheral Select 16 1 read-write P17 Peripheral Select 17 1 read-write P18 Peripheral Select 18 1 read-write P19 Peripheral Select 19 1 read-write P2 Peripheral Select 2 1 read-write P20 Peripheral Select 20 1 read-write P21 Peripheral Select 21 1 read-write P22 Peripheral Select 22 1 read-write P23 Peripheral Select 23 1 read-write P24 Peripheral Select 24 1 read-write P25 Peripheral Select 25 1 read-write P26 Peripheral Select 26 1 read-write P27 Peripheral Select 27 1 read-write P28 Peripheral Select 28 1 read-write P29 Peripheral Select 29 1 read-write P3 Peripheral Select 3 1 read-write P30 Peripheral Select 30 1 read-write P31 Peripheral Select 31 1 read-write P4 Peripheral Select 4 1 read-write P5 Peripheral Select 5 1 read-write P6 Peripheral Select 6 1 read-write P7 Peripheral Select 7 1 read-write P8 Peripheral Select 8 1 read-write P9 Peripheral Select 9 1 read-write ABCDSR1 Peripheral Select Register 0x74 32 read-write n P0 Peripheral Select 0 1 read-write P1 Peripheral Select 1 1 read-write P10 Peripheral Select 10 1 read-write P11 Peripheral Select 11 1 read-write P12 Peripheral Select 12 1 read-write P13 Peripheral Select 13 1 read-write P14 Peripheral Select 14 1 read-write P15 Peripheral Select 15 1 read-write P16 Peripheral Select 16 1 read-write P17 Peripheral Select 17 1 read-write P18 Peripheral Select 18 1 read-write P19 Peripheral Select 19 1 read-write P2 Peripheral Select 2 1 read-write P20 Peripheral Select 20 1 read-write P21 Peripheral Select 21 1 read-write P22 Peripheral Select 22 1 read-write P23 Peripheral Select 23 1 read-write P24 Peripheral Select 24 1 read-write P25 Peripheral Select 25 1 read-write P26 Peripheral Select 26 1 read-write P27 Peripheral Select 27 1 read-write P28 Peripheral Select 28 1 read-write P29 Peripheral Select 29 1 read-write P3 Peripheral Select 3 1 read-write P30 Peripheral Select 30 1 read-write P31 Peripheral Select 31 1 read-write P4 Peripheral Select 4 1 read-write P5 Peripheral Select 5 1 read-write P6 Peripheral Select 6 1 read-write P7 Peripheral Select 7 1 read-write P8 Peripheral Select 8 1 read-write P9 Peripheral Select 9 1 read-write ABCDSR[0] Peripheral Select Register 0xE0 32 read-write n 0x0 0x0 P0 Peripheral Select 0 1 read-write P1 Peripheral Select 1 1 read-write P10 Peripheral Select 10 1 read-write P11 Peripheral Select 11 1 read-write P12 Peripheral Select 12 1 read-write P13 Peripheral Select 13 1 read-write P14 Peripheral Select 14 1 read-write P15 Peripheral Select 15 1 read-write P16 Peripheral Select 16 1 read-write P17 Peripheral Select 17 1 read-write P18 Peripheral Select 18 1 read-write P19 Peripheral Select 19 1 read-write P2 Peripheral Select 2 1 read-write P20 Peripheral Select 20 1 read-write P21 Peripheral Select 21 1 read-write P22 Peripheral Select 22 1 read-write P23 Peripheral Select 23 1 read-write P24 Peripheral Select 24 1 read-write P25 Peripheral Select 25 1 read-write P26 Peripheral Select 26 1 read-write P27 Peripheral Select 27 1 read-write P28 Peripheral Select 28 1 read-write P29 Peripheral Select 29 1 read-write P3 Peripheral Select 3 1 read-write P30 Peripheral Select 30 1 read-write P31 Peripheral Select 31 1 read-write P4 Peripheral Select 4 1 read-write P5 Peripheral Select 5 1 read-write P6 Peripheral Select 6 1 read-write P7 Peripheral Select 7 1 read-write P8 Peripheral Select 8 1 read-write P9 Peripheral Select 9 1 read-write ABCDSR[1] Peripheral Select Register 0x154 32 read-write n 0x0 0x0 P0 Peripheral Select 0 1 read-write P1 Peripheral Select 1 1 read-write P10 Peripheral Select 10 1 read-write P11 Peripheral Select 11 1 read-write P12 Peripheral Select 12 1 read-write P13 Peripheral Select 13 1 read-write P14 Peripheral Select 14 1 read-write P15 Peripheral Select 15 1 read-write P16 Peripheral Select 16 1 read-write P17 Peripheral Select 17 1 read-write P18 Peripheral Select 18 1 read-write P19 Peripheral Select 19 1 read-write P2 Peripheral Select 2 1 read-write P20 Peripheral Select 20 1 read-write P21 Peripheral Select 21 1 read-write P22 Peripheral Select 22 1 read-write P23 Peripheral Select 23 1 read-write P24 Peripheral Select 24 1 read-write P25 Peripheral Select 25 1 read-write P26 Peripheral Select 26 1 read-write P27 Peripheral Select 27 1 read-write P28 Peripheral Select 28 1 read-write P29 Peripheral Select 29 1 read-write P3 Peripheral Select 3 1 read-write P30 Peripheral Select 30 1 read-write P31 Peripheral Select 31 1 read-write P4 Peripheral Select 4 1 read-write P5 Peripheral Select 5 1 read-write P6 Peripheral Select 6 1 read-write P7 Peripheral Select 7 1 read-write P8 Peripheral Select 8 1 read-write P9 Peripheral Select 9 1 read-write AIMDR Additional Interrupt Modes Disable Register 0xB4 32 write-only n 0x0 0x0 P0 Additional Interrupt Modes Disable 0 1 write-only P1 Additional Interrupt Modes Disable 1 1 write-only P10 Additional Interrupt Modes Disable 10 1 write-only P11 Additional Interrupt Modes Disable 11 1 write-only P12 Additional Interrupt Modes Disable 12 1 write-only P13 Additional Interrupt Modes Disable 13 1 write-only P14 Additional Interrupt Modes Disable 14 1 write-only P15 Additional Interrupt Modes Disable 15 1 write-only P16 Additional Interrupt Modes Disable 16 1 write-only P17 Additional Interrupt Modes Disable 17 1 write-only P18 Additional Interrupt Modes Disable 18 1 write-only P19 Additional Interrupt Modes Disable 19 1 write-only P2 Additional Interrupt Modes Disable 2 1 write-only P20 Additional Interrupt Modes Disable 20 1 write-only P21 Additional Interrupt Modes Disable 21 1 write-only P22 Additional Interrupt Modes Disable 22 1 write-only P23 Additional Interrupt Modes Disable 23 1 write-only P24 Additional Interrupt Modes Disable 24 1 write-only P25 Additional Interrupt Modes Disable 25 1 write-only P26 Additional Interrupt Modes Disable 26 1 write-only P27 Additional Interrupt Modes Disable 27 1 write-only P28 Additional Interrupt Modes Disable 28 1 write-only P29 Additional Interrupt Modes Disable 29 1 write-only P3 Additional Interrupt Modes Disable 3 1 write-only P30 Additional Interrupt Modes Disable 30 1 write-only P31 Additional Interrupt Modes Disable 31 1 write-only P4 Additional Interrupt Modes Disable 4 1 write-only P5 Additional Interrupt Modes Disable 5 1 write-only P6 Additional Interrupt Modes Disable 6 1 write-only P7 Additional Interrupt Modes Disable 7 1 write-only P8 Additional Interrupt Modes Disable 8 1 write-only P9 Additional Interrupt Modes Disable 9 1 write-only AIMER Additional Interrupt Modes Enable Register 0xB0 32 write-only n 0x0 0x0 P0 Additional Interrupt Modes Enable 0 1 write-only P1 Additional Interrupt Modes Enable 1 1 write-only P10 Additional Interrupt Modes Enable 10 1 write-only P11 Additional Interrupt Modes Enable 11 1 write-only P12 Additional Interrupt Modes Enable 12 1 write-only P13 Additional Interrupt Modes Enable 13 1 write-only P14 Additional Interrupt Modes Enable 14 1 write-only P15 Additional Interrupt Modes Enable 15 1 write-only P16 Additional Interrupt Modes Enable 16 1 write-only P17 Additional Interrupt Modes Enable 17 1 write-only P18 Additional Interrupt Modes Enable 18 1 write-only P19 Additional Interrupt Modes Enable 19 1 write-only P2 Additional Interrupt Modes Enable 2 1 write-only P20 Additional Interrupt Modes Enable 20 1 write-only P21 Additional Interrupt Modes Enable 21 1 write-only P22 Additional Interrupt Modes Enable 22 1 write-only P23 Additional Interrupt Modes Enable 23 1 write-only P24 Additional Interrupt Modes Enable 24 1 write-only P25 Additional Interrupt Modes Enable 25 1 write-only P26 Additional Interrupt Modes Enable 26 1 write-only P27 Additional Interrupt Modes Enable 27 1 write-only P28 Additional Interrupt Modes Enable 28 1 write-only P29 Additional Interrupt Modes Enable 29 1 write-only P3 Additional Interrupt Modes Enable 3 1 write-only P30 Additional Interrupt Modes Enable 30 1 write-only P31 Additional Interrupt Modes Enable 31 1 write-only P4 Additional Interrupt Modes Enable 4 1 write-only P5 Additional Interrupt Modes Enable 5 1 write-only P6 Additional Interrupt Modes Enable 6 1 write-only P7 Additional Interrupt Modes Enable 7 1 write-only P8 Additional Interrupt Modes Enable 8 1 write-only P9 Additional Interrupt Modes Enable 9 1 write-only AIMMR Additional Interrupt Modes Mask Register 0xB8 32 read-only n 0x0 0x0 P0 Peripheral CD Status 0 1 read-only P1 Peripheral CD Status 1 1 read-only P10 Peripheral CD Status 10 1 read-only P11 Peripheral CD Status 11 1 read-only P12 Peripheral CD Status 12 1 read-only P13 Peripheral CD Status 13 1 read-only P14 Peripheral CD Status 14 1 read-only P15 Peripheral CD Status 15 1 read-only P16 Peripheral CD Status 16 1 read-only P17 Peripheral CD Status 17 1 read-only P18 Peripheral CD Status 18 1 read-only P19 Peripheral CD Status 19 1 read-only P2 Peripheral CD Status 2 1 read-only P20 Peripheral CD Status 20 1 read-only P21 Peripheral CD Status 21 1 read-only P22 Peripheral CD Status 22 1 read-only P23 Peripheral CD Status 23 1 read-only P24 Peripheral CD Status 24 1 read-only P25 Peripheral CD Status 25 1 read-only P26 Peripheral CD Status 26 1 read-only P27 Peripheral CD Status 27 1 read-only P28 Peripheral CD Status 28 1 read-only P29 Peripheral CD Status 29 1 read-only P3 Peripheral CD Status 3 1 read-only P30 Peripheral CD Status 30 1 read-only P31 Peripheral CD Status 31 1 read-only P4 Peripheral CD Status 4 1 read-only P5 Peripheral CD Status 5 1 read-only P6 Peripheral CD Status 6 1 read-only P7 Peripheral CD Status 7 1 read-only P8 Peripheral CD Status 8 1 read-only P9 Peripheral CD Status 9 1 read-only CODR Clear Output Data Register 0x34 32 write-only n 0x0 0x0 P0 Clear Output Data 0 1 write-only P1 Clear Output Data 1 1 write-only P10 Clear Output Data 10 1 write-only P11 Clear Output Data 11 1 write-only P12 Clear Output Data 12 1 write-only P13 Clear Output Data 13 1 write-only P14 Clear Output Data 14 1 write-only P15 Clear Output Data 15 1 write-only P16 Clear Output Data 16 1 write-only P17 Clear Output Data 17 1 write-only P18 Clear Output Data 18 1 write-only P19 Clear Output Data 19 1 write-only P2 Clear Output Data 2 1 write-only P20 Clear Output Data 20 1 write-only P21 Clear Output Data 21 1 write-only P22 Clear Output Data 22 1 write-only P23 Clear Output Data 23 1 write-only P24 Clear Output Data 24 1 write-only P25 Clear Output Data 25 1 write-only P26 Clear Output Data 26 1 write-only P27 Clear Output Data 27 1 write-only P28 Clear Output Data 28 1 write-only P29 Clear Output Data 29 1 write-only P3 Clear Output Data 3 1 write-only P30 Clear Output Data 30 1 write-only P31 Clear Output Data 31 1 write-only P4 Clear Output Data 4 1 write-only P5 Clear Output Data 5 1 write-only P6 Clear Output Data 6 1 write-only P7 Clear Output Data 7 1 write-only P8 Clear Output Data 8 1 write-only P9 Clear Output Data 9 1 write-only ELSR Edge/Level Status Register 0xC8 32 read-only n 0x0 0x0 P0 Edge/Level Interrupt Source Selection 0 1 read-only P1 Edge/Level Interrupt Source Selection 1 1 read-only P10 Edge/Level Interrupt Source Selection 10 1 read-only P11 Edge/Level Interrupt Source Selection 11 1 read-only P12 Edge/Level Interrupt Source Selection 12 1 read-only P13 Edge/Level Interrupt Source Selection 13 1 read-only P14 Edge/Level Interrupt Source Selection 14 1 read-only P15 Edge/Level Interrupt Source Selection 15 1 read-only P16 Edge/Level Interrupt Source Selection 16 1 read-only P17 Edge/Level Interrupt Source Selection 17 1 read-only P18 Edge/Level Interrupt Source Selection 18 1 read-only P19 Edge/Level Interrupt Source Selection 19 1 read-only P2 Edge/Level Interrupt Source Selection 2 1 read-only P20 Edge/Level Interrupt Source Selection 20 1 read-only P21 Edge/Level Interrupt Source Selection 21 1 read-only P22 Edge/Level Interrupt Source Selection 22 1 read-only P23 Edge/Level Interrupt Source Selection 23 1 read-only P24 Edge/Level Interrupt Source Selection 24 1 read-only P25 Edge/Level Interrupt Source Selection 25 1 read-only P26 Edge/Level Interrupt Source Selection 26 1 read-only P27 Edge/Level Interrupt Source Selection 27 1 read-only P28 Edge/Level Interrupt Source Selection 28 1 read-only P29 Edge/Level Interrupt Source Selection 29 1 read-only P3 Edge/Level Interrupt Source Selection 3 1 read-only P30 Edge/Level Interrupt Source Selection 30 1 read-only P31 Edge/Level Interrupt Source Selection 31 1 read-only P4 Edge/Level Interrupt Source Selection 4 1 read-only P5 Edge/Level Interrupt Source Selection 5 1 read-only P6 Edge/Level Interrupt Source Selection 6 1 read-only P7 Edge/Level Interrupt Source Selection 7 1 read-only P8 Edge/Level Interrupt Source Selection 8 1 read-only P9 Edge/Level Interrupt Source Selection 9 1 read-only ESR Edge Select Register 0xC0 32 write-only n 0x0 0x0 P0 Edge Interrupt Selection 0 1 write-only P1 Edge Interrupt Selection 1 1 write-only P10 Edge Interrupt Selection 10 1 write-only P11 Edge Interrupt Selection 11 1 write-only P12 Edge Interrupt Selection 12 1 write-only P13 Edge Interrupt Selection 13 1 write-only P14 Edge Interrupt Selection 14 1 write-only P15 Edge Interrupt Selection 15 1 write-only P16 Edge Interrupt Selection 16 1 write-only P17 Edge Interrupt Selection 17 1 write-only P18 Edge Interrupt Selection 18 1 write-only P19 Edge Interrupt Selection 19 1 write-only P2 Edge Interrupt Selection 2 1 write-only P20 Edge Interrupt Selection 20 1 write-only P21 Edge Interrupt Selection 21 1 write-only P22 Edge Interrupt Selection 22 1 write-only P23 Edge Interrupt Selection 23 1 write-only P24 Edge Interrupt Selection 24 1 write-only P25 Edge Interrupt Selection 25 1 write-only P26 Edge Interrupt Selection 26 1 write-only P27 Edge Interrupt Selection 27 1 write-only P28 Edge Interrupt Selection 28 1 write-only P29 Edge Interrupt Selection 29 1 write-only P3 Edge Interrupt Selection 3 1 write-only P30 Edge Interrupt Selection 30 1 write-only P31 Edge Interrupt Selection 31 1 write-only P4 Edge Interrupt Selection 4 1 write-only P5 Edge Interrupt Selection 5 1 write-only P6 Edge Interrupt Selection 6 1 write-only P7 Edge Interrupt Selection 7 1 write-only P8 Edge Interrupt Selection 8 1 write-only P9 Edge Interrupt Selection 9 1 write-only FELLSR Falling Edge/Low-Level Select Register 0xD0 32 write-only n 0x0 0x0 P0 Falling Edge/Low-Level Interrupt Selection 0 1 write-only P1 Falling Edge/Low-Level Interrupt Selection 1 1 write-only P10 Falling Edge/Low-Level Interrupt Selection 10 1 write-only P11 Falling Edge/Low-Level Interrupt Selection 11 1 write-only P12 Falling Edge/Low-Level Interrupt Selection 12 1 write-only P13 Falling Edge/Low-Level Interrupt Selection 13 1 write-only P14 Falling Edge/Low-Level Interrupt Selection 14 1 write-only P15 Falling Edge/Low-Level Interrupt Selection 15 1 write-only P16 Falling Edge/Low-Level Interrupt Selection 16 1 write-only P17 Falling Edge/Low-Level Interrupt Selection 17 1 write-only P18 Falling Edge/Low-Level Interrupt Selection 18 1 write-only P19 Falling Edge/Low-Level Interrupt Selection 19 1 write-only P2 Falling Edge/Low-Level Interrupt Selection 2 1 write-only P20 Falling Edge/Low-Level Interrupt Selection 20 1 write-only P21 Falling Edge/Low-Level Interrupt Selection 21 1 write-only P22 Falling Edge/Low-Level Interrupt Selection 22 1 write-only P23 Falling Edge/Low-Level Interrupt Selection 23 1 write-only P24 Falling Edge/Low-Level Interrupt Selection 24 1 write-only P25 Falling Edge/Low-Level Interrupt Selection 25 1 write-only P26 Falling Edge/Low-Level Interrupt Selection 26 1 write-only P27 Falling Edge/Low-Level Interrupt Selection 27 1 write-only P28 Falling Edge/Low-Level Interrupt Selection 28 1 write-only P29 Falling Edge/Low-Level Interrupt Selection 29 1 write-only P3 Falling Edge/Low-Level Interrupt Selection 3 1 write-only P30 Falling Edge/Low-Level Interrupt Selection 30 1 write-only P31 Falling Edge/Low-Level Interrupt Selection 31 1 write-only P4 Falling Edge/Low-Level Interrupt Selection 4 1 write-only P5 Falling Edge/Low-Level Interrupt Selection 5 1 write-only P6 Falling Edge/Low-Level Interrupt Selection 6 1 write-only P7 Falling Edge/Low-Level Interrupt Selection 7 1 write-only P8 Falling Edge/Low-Level Interrupt Selection 8 1 write-only P9 Falling Edge/Low-Level Interrupt Selection 9 1 write-only FRLHSR Fall/Rise - Low/High Status Register 0xD8 32 read-only n 0x0 0x0 P0 Edge /Level Interrupt Source Selection 0 1 read-only P1 Edge /Level Interrupt Source Selection 1 1 read-only P10 Edge /Level Interrupt Source Selection 10 1 read-only P11 Edge /Level Interrupt Source Selection 11 1 read-only P12 Edge /Level Interrupt Source Selection 12 1 read-only P13 Edge /Level Interrupt Source Selection 13 1 read-only P14 Edge /Level Interrupt Source Selection 14 1 read-only P15 Edge /Level Interrupt Source Selection 15 1 read-only P16 Edge /Level Interrupt Source Selection 16 1 read-only P17 Edge /Level Interrupt Source Selection 17 1 read-only P18 Edge /Level Interrupt Source Selection 18 1 read-only P19 Edge /Level Interrupt Source Selection 19 1 read-only P2 Edge /Level Interrupt Source Selection 2 1 read-only P20 Edge /Level Interrupt Source Selection 20 1 read-only P21 Edge /Level Interrupt Source Selection 21 1 read-only P22 Edge /Level Interrupt Source Selection 22 1 read-only P23 Edge /Level Interrupt Source Selection 23 1 read-only P24 Edge /Level Interrupt Source Selection 24 1 read-only P25 Edge /Level Interrupt Source Selection 25 1 read-only P26 Edge /Level Interrupt Source Selection 26 1 read-only P27 Edge /Level Interrupt Source Selection 27 1 read-only P28 Edge /Level Interrupt Source Selection 28 1 read-only P29 Edge /Level Interrupt Source Selection 29 1 read-only P3 Edge /Level Interrupt Source Selection 3 1 read-only P30 Edge /Level Interrupt Source Selection 30 1 read-only P31 Edge /Level Interrupt Source Selection 31 1 read-only P4 Edge /Level Interrupt Source Selection 4 1 read-only P5 Edge /Level Interrupt Source Selection 5 1 read-only P6 Edge /Level Interrupt Source Selection 6 1 read-only P7 Edge /Level Interrupt Source Selection 7 1 read-only P8 Edge /Level Interrupt Source Selection 8 1 read-only P9 Edge /Level Interrupt Source Selection 9 1 read-only IDR Interrupt Disable Register 0x44 32 write-only n 0x0 0x0 P0 Input Change Interrupt Disable 0 1 write-only P1 Input Change Interrupt Disable 1 1 write-only P10 Input Change Interrupt Disable 10 1 write-only P11 Input Change Interrupt Disable 11 1 write-only P12 Input Change Interrupt Disable 12 1 write-only P13 Input Change Interrupt Disable 13 1 write-only P14 Input Change Interrupt Disable 14 1 write-only P15 Input Change Interrupt Disable 15 1 write-only P16 Input Change Interrupt Disable 16 1 write-only P17 Input Change Interrupt Disable 17 1 write-only P18 Input Change Interrupt Disable 18 1 write-only P19 Input Change Interrupt Disable 19 1 write-only P2 Input Change Interrupt Disable 2 1 write-only P20 Input Change Interrupt Disable 20 1 write-only P21 Input Change Interrupt Disable 21 1 write-only P22 Input Change Interrupt Disable 22 1 write-only P23 Input Change Interrupt Disable 23 1 write-only P24 Input Change Interrupt Disable 24 1 write-only P25 Input Change Interrupt Disable 25 1 write-only P26 Input Change Interrupt Disable 26 1 write-only P27 Input Change Interrupt Disable 27 1 write-only P28 Input Change Interrupt Disable 28 1 write-only P29 Input Change Interrupt Disable 29 1 write-only P3 Input Change Interrupt Disable 3 1 write-only P30 Input Change Interrupt Disable 30 1 write-only P31 Input Change Interrupt Disable 31 1 write-only P4 Input Change Interrupt Disable 4 1 write-only P5 Input Change Interrupt Disable 5 1 write-only P6 Input Change Interrupt Disable 6 1 write-only P7 Input Change Interrupt Disable 7 1 write-only P8 Input Change Interrupt Disable 8 1 write-only P9 Input Change Interrupt Disable 9 1 write-only IER Interrupt Enable Register 0x40 32 write-only n 0x0 0x0 P0 Input Change Interrupt Enable 0 1 write-only P1 Input Change Interrupt Enable 1 1 write-only P10 Input Change Interrupt Enable 10 1 write-only P11 Input Change Interrupt Enable 11 1 write-only P12 Input Change Interrupt Enable 12 1 write-only P13 Input Change Interrupt Enable 13 1 write-only P14 Input Change Interrupt Enable 14 1 write-only P15 Input Change Interrupt Enable 15 1 write-only P16 Input Change Interrupt Enable 16 1 write-only P17 Input Change Interrupt Enable 17 1 write-only P18 Input Change Interrupt Enable 18 1 write-only P19 Input Change Interrupt Enable 19 1 write-only P2 Input Change Interrupt Enable 2 1 write-only P20 Input Change Interrupt Enable 20 1 write-only P21 Input Change Interrupt Enable 21 1 write-only P22 Input Change Interrupt Enable 22 1 write-only P23 Input Change Interrupt Enable 23 1 write-only P24 Input Change Interrupt Enable 24 1 write-only P25 Input Change Interrupt Enable 25 1 write-only P26 Input Change Interrupt Enable 26 1 write-only P27 Input Change Interrupt Enable 27 1 write-only P28 Input Change Interrupt Enable 28 1 write-only P29 Input Change Interrupt Enable 29 1 write-only P3 Input Change Interrupt Enable 3 1 write-only P30 Input Change Interrupt Enable 30 1 write-only P31 Input Change Interrupt Enable 31 1 write-only P4 Input Change Interrupt Enable 4 1 write-only P5 Input Change Interrupt Enable 5 1 write-only P6 Input Change Interrupt Enable 6 1 write-only P7 Input Change Interrupt Enable 7 1 write-only P8 Input Change Interrupt Enable 8 1 write-only P9 Input Change Interrupt Enable 9 1 write-only IFDR Glitch Input Filter Disable Register 0x24 32 write-only n 0x0 0x0 P0 Input Filter Disable 0 1 write-only P1 Input Filter Disable 1 1 write-only P10 Input Filter Disable 10 1 write-only P11 Input Filter Disable 11 1 write-only P12 Input Filter Disable 12 1 write-only P13 Input Filter Disable 13 1 write-only P14 Input Filter Disable 14 1 write-only P15 Input Filter Disable 15 1 write-only P16 Input Filter Disable 16 1 write-only P17 Input Filter Disable 17 1 write-only P18 Input Filter Disable 18 1 write-only P19 Input Filter Disable 19 1 write-only P2 Input Filter Disable 2 1 write-only P20 Input Filter Disable 20 1 write-only P21 Input Filter Disable 21 1 write-only P22 Input Filter Disable 22 1 write-only P23 Input Filter Disable 23 1 write-only P24 Input Filter Disable 24 1 write-only P25 Input Filter Disable 25 1 write-only P26 Input Filter Disable 26 1 write-only P27 Input Filter Disable 27 1 write-only P28 Input Filter Disable 28 1 write-only P29 Input Filter Disable 29 1 write-only P3 Input Filter Disable 3 1 write-only P30 Input Filter Disable 30 1 write-only P31 Input Filter Disable 31 1 write-only P4 Input Filter Disable 4 1 write-only P5 Input Filter Disable 5 1 write-only P6 Input Filter Disable 6 1 write-only P7 Input Filter Disable 7 1 write-only P8 Input Filter Disable 8 1 write-only P9 Input Filter Disable 9 1 write-only IFER Glitch Input Filter Enable Register 0x20 32 write-only n 0x0 0x0 P0 Input Filter Enable 0 1 write-only P1 Input Filter Enable 1 1 write-only P10 Input Filter Enable 10 1 write-only P11 Input Filter Enable 11 1 write-only P12 Input Filter Enable 12 1 write-only P13 Input Filter Enable 13 1 write-only P14 Input Filter Enable 14 1 write-only P15 Input Filter Enable 15 1 write-only P16 Input Filter Enable 16 1 write-only P17 Input Filter Enable 17 1 write-only P18 Input Filter Enable 18 1 write-only P19 Input Filter Enable 19 1 write-only P2 Input Filter Enable 2 1 write-only P20 Input Filter Enable 20 1 write-only P21 Input Filter Enable 21 1 write-only P22 Input Filter Enable 22 1 write-only P23 Input Filter Enable 23 1 write-only P24 Input Filter Enable 24 1 write-only P25 Input Filter Enable 25 1 write-only P26 Input Filter Enable 26 1 write-only P27 Input Filter Enable 27 1 write-only P28 Input Filter Enable 28 1 write-only P29 Input Filter Enable 29 1 write-only P3 Input Filter Enable 3 1 write-only P30 Input Filter Enable 30 1 write-only P31 Input Filter Enable 31 1 write-only P4 Input Filter Enable 4 1 write-only P5 Input Filter Enable 5 1 write-only P6 Input Filter Enable 6 1 write-only P7 Input Filter Enable 7 1 write-only P8 Input Filter Enable 8 1 write-only P9 Input Filter Enable 9 1 write-only IFSCDR Input Filter Slow Clock Disable Register 0x80 32 write-only n 0x0 0x0 P0 PIO Clock Glitch Filtering Select 0 1 write-only P1 PIO Clock Glitch Filtering Select 1 1 write-only P10 PIO Clock Glitch Filtering Select 10 1 write-only P11 PIO Clock Glitch Filtering Select 11 1 write-only P12 PIO Clock Glitch Filtering Select 12 1 write-only P13 PIO Clock Glitch Filtering Select 13 1 write-only P14 PIO Clock Glitch Filtering Select 14 1 write-only P15 PIO Clock Glitch Filtering Select 15 1 write-only P16 PIO Clock Glitch Filtering Select 16 1 write-only P17 PIO Clock Glitch Filtering Select 17 1 write-only P18 PIO Clock Glitch Filtering Select 18 1 write-only P19 PIO Clock Glitch Filtering Select 19 1 write-only P2 PIO Clock Glitch Filtering Select 2 1 write-only P20 PIO Clock Glitch Filtering Select 20 1 write-only P21 PIO Clock Glitch Filtering Select 21 1 write-only P22 PIO Clock Glitch Filtering Select 22 1 write-only P23 PIO Clock Glitch Filtering Select 23 1 write-only P24 PIO Clock Glitch Filtering Select 24 1 write-only P25 PIO Clock Glitch Filtering Select 25 1 write-only P26 PIO Clock Glitch Filtering Select 26 1 write-only P27 PIO Clock Glitch Filtering Select 27 1 write-only P28 PIO Clock Glitch Filtering Select 28 1 write-only P29 PIO Clock Glitch Filtering Select 29 1 write-only P3 PIO Clock Glitch Filtering Select 3 1 write-only P30 PIO Clock Glitch Filtering Select 30 1 write-only P31 PIO Clock Glitch Filtering Select 31 1 write-only P4 PIO Clock Glitch Filtering Select 4 1 write-only P5 PIO Clock Glitch Filtering Select 5 1 write-only P6 PIO Clock Glitch Filtering Select 6 1 write-only P7 PIO Clock Glitch Filtering Select 7 1 write-only P8 PIO Clock Glitch Filtering Select 8 1 write-only P9 PIO Clock Glitch Filtering Select 9 1 write-only IFSCER Input Filter Slow Clock Enable Register 0x84 32 write-only n 0x0 0x0 P0 Debouncing Filtering Select 0 1 write-only P1 Debouncing Filtering Select 1 1 write-only P10 Debouncing Filtering Select 10 1 write-only P11 Debouncing Filtering Select 11 1 write-only P12 Debouncing Filtering Select 12 1 write-only P13 Debouncing Filtering Select 13 1 write-only P14 Debouncing Filtering Select 14 1 write-only P15 Debouncing Filtering Select 15 1 write-only P16 Debouncing Filtering Select 16 1 write-only P17 Debouncing Filtering Select 17 1 write-only P18 Debouncing Filtering Select 18 1 write-only P19 Debouncing Filtering Select 19 1 write-only P2 Debouncing Filtering Select 2 1 write-only P20 Debouncing Filtering Select 20 1 write-only P21 Debouncing Filtering Select 21 1 write-only P22 Debouncing Filtering Select 22 1 write-only P23 Debouncing Filtering Select 23 1 write-only P24 Debouncing Filtering Select 24 1 write-only P25 Debouncing Filtering Select 25 1 write-only P26 Debouncing Filtering Select 26 1 write-only P27 Debouncing Filtering Select 27 1 write-only P28 Debouncing Filtering Select 28 1 write-only P29 Debouncing Filtering Select 29 1 write-only P3 Debouncing Filtering Select 3 1 write-only P30 Debouncing Filtering Select 30 1 write-only P31 Debouncing Filtering Select 31 1 write-only P4 Debouncing Filtering Select 4 1 write-only P5 Debouncing Filtering Select 5 1 write-only P6 Debouncing Filtering Select 6 1 write-only P7 Debouncing Filtering Select 7 1 write-only P8 Debouncing Filtering Select 8 1 write-only P9 Debouncing Filtering Select 9 1 write-only IFSCSR Input Filter Slow Clock Status Register 0x88 32 read-only n 0x0 0x0 P0 Glitch or Debouncing Filter Selection Status 0 1 read-only P1 Glitch or Debouncing Filter Selection Status 1 1 read-only P10 Glitch or Debouncing Filter Selection Status 10 1 read-only P11 Glitch or Debouncing Filter Selection Status 11 1 read-only P12 Glitch or Debouncing Filter Selection Status 12 1 read-only P13 Glitch or Debouncing Filter Selection Status 13 1 read-only P14 Glitch or Debouncing Filter Selection Status 14 1 read-only P15 Glitch or Debouncing Filter Selection Status 15 1 read-only P16 Glitch or Debouncing Filter Selection Status 16 1 read-only P17 Glitch or Debouncing Filter Selection Status 17 1 read-only P18 Glitch or Debouncing Filter Selection Status 18 1 read-only P19 Glitch or Debouncing Filter Selection Status 19 1 read-only P2 Glitch or Debouncing Filter Selection Status 2 1 read-only P20 Glitch or Debouncing Filter Selection Status 20 1 read-only P21 Glitch or Debouncing Filter Selection Status 21 1 read-only P22 Glitch or Debouncing Filter Selection Status 22 1 read-only P23 Glitch or Debouncing Filter Selection Status 23 1 read-only P24 Glitch or Debouncing Filter Selection Status 24 1 read-only P25 Glitch or Debouncing Filter Selection Status 25 1 read-only P26 Glitch or Debouncing Filter Selection Status 26 1 read-only P27 Glitch or Debouncing Filter Selection Status 27 1 read-only P28 Glitch or Debouncing Filter Selection Status 28 1 read-only P29 Glitch or Debouncing Filter Selection Status 29 1 read-only P3 Glitch or Debouncing Filter Selection Status 3 1 read-only P30 Glitch or Debouncing Filter Selection Status 30 1 read-only P31 Glitch or Debouncing Filter Selection Status 31 1 read-only P4 Glitch or Debouncing Filter Selection Status 4 1 read-only P5 Glitch or Debouncing Filter Selection Status 5 1 read-only P6 Glitch or Debouncing Filter Selection Status 6 1 read-only P7 Glitch or Debouncing Filter Selection Status 7 1 read-only P8 Glitch or Debouncing Filter Selection Status 8 1 read-only P9 Glitch or Debouncing Filter Selection Status 9 1 read-only IFSR Glitch Input Filter Status Register 0x28 32 read-only n 0x0 0x0 P0 Input Filer Status 0 1 read-only P1 Input Filer Status 1 1 read-only P10 Input Filer Status 10 1 read-only P11 Input Filer Status 11 1 read-only P12 Input Filer Status 12 1 read-only P13 Input Filer Status 13 1 read-only P14 Input Filer Status 14 1 read-only P15 Input Filer Status 15 1 read-only P16 Input Filer Status 16 1 read-only P17 Input Filer Status 17 1 read-only P18 Input Filer Status 18 1 read-only P19 Input Filer Status 19 1 read-only P2 Input Filer Status 2 1 read-only P20 Input Filer Status 20 1 read-only P21 Input Filer Status 21 1 read-only P22 Input Filer Status 22 1 read-only P23 Input Filer Status 23 1 read-only P24 Input Filer Status 24 1 read-only P25 Input Filer Status 25 1 read-only P26 Input Filer Status 26 1 read-only P27 Input Filer Status 27 1 read-only P28 Input Filer Status 28 1 read-only P29 Input Filer Status 29 1 read-only P3 Input Filer Status 3 1 read-only P30 Input Filer Status 30 1 read-only P31 Input Filer Status 31 1 read-only P4 Input Filer Status 4 1 read-only P5 Input Filer Status 5 1 read-only P6 Input Filer Status 6 1 read-only P7 Input Filer Status 7 1 read-only P8 Input Filer Status 8 1 read-only P9 Input Filer Status 9 1 read-only IMR Interrupt Mask Register 0x48 32 read-only n 0x0 0x0 P0 Input Change Interrupt Mask 0 1 read-only P1 Input Change Interrupt Mask 1 1 read-only P10 Input Change Interrupt Mask 10 1 read-only P11 Input Change Interrupt Mask 11 1 read-only P12 Input Change Interrupt Mask 12 1 read-only P13 Input Change Interrupt Mask 13 1 read-only P14 Input Change Interrupt Mask 14 1 read-only P15 Input Change Interrupt Mask 15 1 read-only P16 Input Change Interrupt Mask 16 1 read-only P17 Input Change Interrupt Mask 17 1 read-only P18 Input Change Interrupt Mask 18 1 read-only P19 Input Change Interrupt Mask 19 1 read-only P2 Input Change Interrupt Mask 2 1 read-only P20 Input Change Interrupt Mask 20 1 read-only P21 Input Change Interrupt Mask 21 1 read-only P22 Input Change Interrupt Mask 22 1 read-only P23 Input Change Interrupt Mask 23 1 read-only P24 Input Change Interrupt Mask 24 1 read-only P25 Input Change Interrupt Mask 25 1 read-only P26 Input Change Interrupt Mask 26 1 read-only P27 Input Change Interrupt Mask 27 1 read-only P28 Input Change Interrupt Mask 28 1 read-only P29 Input Change Interrupt Mask 29 1 read-only P3 Input Change Interrupt Mask 3 1 read-only P30 Input Change Interrupt Mask 30 1 read-only P31 Input Change Interrupt Mask 31 1 read-only P4 Input Change Interrupt Mask 4 1 read-only P5 Input Change Interrupt Mask 5 1 read-only P6 Input Change Interrupt Mask 6 1 read-only P7 Input Change Interrupt Mask 7 1 read-only P8 Input Change Interrupt Mask 8 1 read-only P9 Input Change Interrupt Mask 9 1 read-only ISR Interrupt Status Register 0x4C 32 read-only n 0x0 0x0 P0 Input Change Interrupt Status 0 1 read-only P1 Input Change Interrupt Status 1 1 read-only P10 Input Change Interrupt Status 10 1 read-only P11 Input Change Interrupt Status 11 1 read-only P12 Input Change Interrupt Status 12 1 read-only P13 Input Change Interrupt Status 13 1 read-only P14 Input Change Interrupt Status 14 1 read-only P15 Input Change Interrupt Status 15 1 read-only P16 Input Change Interrupt Status 16 1 read-only P17 Input Change Interrupt Status 17 1 read-only P18 Input Change Interrupt Status 18 1 read-only P19 Input Change Interrupt Status 19 1 read-only P2 Input Change Interrupt Status 2 1 read-only P20 Input Change Interrupt Status 20 1 read-only P21 Input Change Interrupt Status 21 1 read-only P22 Input Change Interrupt Status 22 1 read-only P23 Input Change Interrupt Status 23 1 read-only P24 Input Change Interrupt Status 24 1 read-only P25 Input Change Interrupt Status 25 1 read-only P26 Input Change Interrupt Status 26 1 read-only P27 Input Change Interrupt Status 27 1 read-only P28 Input Change Interrupt Status 28 1 read-only P29 Input Change Interrupt Status 29 1 read-only P3 Input Change Interrupt Status 3 1 read-only P30 Input Change Interrupt Status 30 1 read-only P31 Input Change Interrupt Status 31 1 read-only P4 Input Change Interrupt Status 4 1 read-only P5 Input Change Interrupt Status 5 1 read-only P6 Input Change Interrupt Status 6 1 read-only P7 Input Change Interrupt Status 7 1 read-only P8 Input Change Interrupt Status 8 1 read-only P9 Input Change Interrupt Status 9 1 read-only LSR Level Select Register 0xC4 32 write-only n 0x0 0x0 P0 Level Interrupt Selection 0 1 write-only P1 Level Interrupt Selection 1 1 write-only P10 Level Interrupt Selection 10 1 write-only P11 Level Interrupt Selection 11 1 write-only P12 Level Interrupt Selection 12 1 write-only P13 Level Interrupt Selection 13 1 write-only P14 Level Interrupt Selection 14 1 write-only P15 Level Interrupt Selection 15 1 write-only P16 Level Interrupt Selection 16 1 write-only P17 Level Interrupt Selection 17 1 write-only P18 Level Interrupt Selection 18 1 write-only P19 Level Interrupt Selection 19 1 write-only P2 Level Interrupt Selection 2 1 write-only P20 Level Interrupt Selection 20 1 write-only P21 Level Interrupt Selection 21 1 write-only P22 Level Interrupt Selection 22 1 write-only P23 Level Interrupt Selection 23 1 write-only P24 Level Interrupt Selection 24 1 write-only P25 Level Interrupt Selection 25 1 write-only P26 Level Interrupt Selection 26 1 write-only P27 Level Interrupt Selection 27 1 write-only P28 Level Interrupt Selection 28 1 write-only P29 Level Interrupt Selection 29 1 write-only P3 Level Interrupt Selection 3 1 write-only P30 Level Interrupt Selection 30 1 write-only P31 Level Interrupt Selection 31 1 write-only P4 Level Interrupt Selection 4 1 write-only P5 Level Interrupt Selection 5 1 write-only P6 Level Interrupt Selection 6 1 write-only P7 Level Interrupt Selection 7 1 write-only P8 Level Interrupt Selection 8 1 write-only P9 Level Interrupt Selection 9 1 write-only MDDR Multi-driver Disable Register 0x54 32 write-only n 0x0 0x0 P0 Multi-Drive Disable 0 1 write-only P1 Multi-Drive Disable 1 1 write-only P10 Multi-Drive Disable 10 1 write-only P11 Multi-Drive Disable 11 1 write-only P12 Multi-Drive Disable 12 1 write-only P13 Multi-Drive Disable 13 1 write-only P14 Multi-Drive Disable 14 1 write-only P15 Multi-Drive Disable 15 1 write-only P16 Multi-Drive Disable 16 1 write-only P17 Multi-Drive Disable 17 1 write-only P18 Multi-Drive Disable 18 1 write-only P19 Multi-Drive Disable 19 1 write-only P2 Multi-Drive Disable 2 1 write-only P20 Multi-Drive Disable 20 1 write-only P21 Multi-Drive Disable 21 1 write-only P22 Multi-Drive Disable 22 1 write-only P23 Multi-Drive Disable 23 1 write-only P24 Multi-Drive Disable 24 1 write-only P25 Multi-Drive Disable 25 1 write-only P26 Multi-Drive Disable 26 1 write-only P27 Multi-Drive Disable 27 1 write-only P28 Multi-Drive Disable 28 1 write-only P29 Multi-Drive Disable 29 1 write-only P3 Multi-Drive Disable 3 1 write-only P30 Multi-Drive Disable 30 1 write-only P31 Multi-Drive Disable 31 1 write-only P4 Multi-Drive Disable 4 1 write-only P5 Multi-Drive Disable 5 1 write-only P6 Multi-Drive Disable 6 1 write-only P7 Multi-Drive Disable 7 1 write-only P8 Multi-Drive Disable 8 1 write-only P9 Multi-Drive Disable 9 1 write-only MDER Multi-driver Enable Register 0x50 32 write-only n 0x0 0x0 P0 Multi-Drive Enable 0 1 write-only P1 Multi-Drive Enable 1 1 write-only P10 Multi-Drive Enable 10 1 write-only P11 Multi-Drive Enable 11 1 write-only P12 Multi-Drive Enable 12 1 write-only P13 Multi-Drive Enable 13 1 write-only P14 Multi-Drive Enable 14 1 write-only P15 Multi-Drive Enable 15 1 write-only P16 Multi-Drive Enable 16 1 write-only P17 Multi-Drive Enable 17 1 write-only P18 Multi-Drive Enable 18 1 write-only P19 Multi-Drive Enable 19 1 write-only P2 Multi-Drive Enable 2 1 write-only P20 Multi-Drive Enable 20 1 write-only P21 Multi-Drive Enable 21 1 write-only P22 Multi-Drive Enable 22 1 write-only P23 Multi-Drive Enable 23 1 write-only P24 Multi-Drive Enable 24 1 write-only P25 Multi-Drive Enable 25 1 write-only P26 Multi-Drive Enable 26 1 write-only P27 Multi-Drive Enable 27 1 write-only P28 Multi-Drive Enable 28 1 write-only P29 Multi-Drive Enable 29 1 write-only P3 Multi-Drive Enable 3 1 write-only P30 Multi-Drive Enable 30 1 write-only P31 Multi-Drive Enable 31 1 write-only P4 Multi-Drive Enable 4 1 write-only P5 Multi-Drive Enable 5 1 write-only P6 Multi-Drive Enable 6 1 write-only P7 Multi-Drive Enable 7 1 write-only P8 Multi-Drive Enable 8 1 write-only P9 Multi-Drive Enable 9 1 write-only MDSR Multi-driver Status Register 0x58 32 read-only n 0x0 0x0 P0 Multi-Drive Status 0 1 read-only P1 Multi-Drive Status 1 1 read-only P10 Multi-Drive Status 10 1 read-only P11 Multi-Drive Status 11 1 read-only P12 Multi-Drive Status 12 1 read-only P13 Multi-Drive Status 13 1 read-only P14 Multi-Drive Status 14 1 read-only P15 Multi-Drive Status 15 1 read-only P16 Multi-Drive Status 16 1 read-only P17 Multi-Drive Status 17 1 read-only P18 Multi-Drive Status 18 1 read-only P19 Multi-Drive Status 19 1 read-only P2 Multi-Drive Status 2 1 read-only P20 Multi-Drive Status 20 1 read-only P21 Multi-Drive Status 21 1 read-only P22 Multi-Drive Status 22 1 read-only P23 Multi-Drive Status 23 1 read-only P24 Multi-Drive Status 24 1 read-only P25 Multi-Drive Status 25 1 read-only P26 Multi-Drive Status 26 1 read-only P27 Multi-Drive Status 27 1 read-only P28 Multi-Drive Status 28 1 read-only P29 Multi-Drive Status 29 1 read-only P3 Multi-Drive Status 3 1 read-only P30 Multi-Drive Status 30 1 read-only P31 Multi-Drive Status 31 1 read-only P4 Multi-Drive Status 4 1 read-only P5 Multi-Drive Status 5 1 read-only P6 Multi-Drive Status 6 1 read-only P7 Multi-Drive Status 7 1 read-only P8 Multi-Drive Status 8 1 read-only P9 Multi-Drive Status 9 1 read-only ODR Output Disable Register 0x14 32 write-only n 0x0 0x0 P0 Output Disable 0 1 write-only P1 Output Disable 1 1 write-only P10 Output Disable 10 1 write-only P11 Output Disable 11 1 write-only P12 Output Disable 12 1 write-only P13 Output Disable 13 1 write-only P14 Output Disable 14 1 write-only P15 Output Disable 15 1 write-only P16 Output Disable 16 1 write-only P17 Output Disable 17 1 write-only P18 Output Disable 18 1 write-only P19 Output Disable 19 1 write-only P2 Output Disable 2 1 write-only P20 Output Disable 20 1 write-only P21 Output Disable 21 1 write-only P22 Output Disable 22 1 write-only P23 Output Disable 23 1 write-only P24 Output Disable 24 1 write-only P25 Output Disable 25 1 write-only P26 Output Disable 26 1 write-only P27 Output Disable 27 1 write-only P28 Output Disable 28 1 write-only P29 Output Disable 29 1 write-only P3 Output Disable 3 1 write-only P30 Output Disable 30 1 write-only P31 Output Disable 31 1 write-only P4 Output Disable 4 1 write-only P5 Output Disable 5 1 write-only P6 Output Disable 6 1 write-only P7 Output Disable 7 1 write-only P8 Output Disable 8 1 write-only P9 Output Disable 9 1 write-only ODSR Output Data Status Register 0x38 32 read-write n 0x0 0x0 P0 Output Data Status 0 1 read-write P1 Output Data Status 1 1 read-write P10 Output Data Status 10 1 read-write P11 Output Data Status 11 1 read-write P12 Output Data Status 12 1 read-write P13 Output Data Status 13 1 read-write P14 Output Data Status 14 1 read-write P15 Output Data Status 15 1 read-write P16 Output Data Status 16 1 read-write P17 Output Data Status 17 1 read-write P18 Output Data Status 18 1 read-write P19 Output Data Status 19 1 read-write P2 Output Data Status 2 1 read-write P20 Output Data Status 20 1 read-write P21 Output Data Status 21 1 read-write P22 Output Data Status 22 1 read-write P23 Output Data Status 23 1 read-write P24 Output Data Status 24 1 read-write P25 Output Data Status 25 1 read-write P26 Output Data Status 26 1 read-write P27 Output Data Status 27 1 read-write P28 Output Data Status 28 1 read-write P29 Output Data Status 29 1 read-write P3 Output Data Status 3 1 read-write P30 Output Data Status 30 1 read-write P31 Output Data Status 31 1 read-write P4 Output Data Status 4 1 read-write P5 Output Data Status 5 1 read-write P6 Output Data Status 6 1 read-write P7 Output Data Status 7 1 read-write P8 Output Data Status 8 1 read-write P9 Output Data Status 9 1 read-write OER Output Enable Register 0x10 32 write-only n 0x0 0x0 P0 Output Enable 0 1 write-only P1 Output Enable 1 1 write-only P10 Output Enable 10 1 write-only P11 Output Enable 11 1 write-only P12 Output Enable 12 1 write-only P13 Output Enable 13 1 write-only P14 Output Enable 14 1 write-only P15 Output Enable 15 1 write-only P16 Output Enable 16 1 write-only P17 Output Enable 17 1 write-only P18 Output Enable 18 1 write-only P19 Output Enable 19 1 write-only P2 Output Enable 2 1 write-only P20 Output Enable 20 1 write-only P21 Output Enable 21 1 write-only P22 Output Enable 22 1 write-only P23 Output Enable 23 1 write-only P24 Output Enable 24 1 write-only P25 Output Enable 25 1 write-only P26 Output Enable 26 1 write-only P27 Output Enable 27 1 write-only P28 Output Enable 28 1 write-only P29 Output Enable 29 1 write-only P3 Output Enable 3 1 write-only P30 Output Enable 30 1 write-only P31 Output Enable 31 1 write-only P4 Output Enable 4 1 write-only P5 Output Enable 5 1 write-only P6 Output Enable 6 1 write-only P7 Output Enable 7 1 write-only P8 Output Enable 8 1 write-only P9 Output Enable 9 1 write-only OSR Output Status Register 0x18 32 read-only n 0x0 0x0 P0 Output Status 0 1 read-only P1 Output Status 1 1 read-only P10 Output Status 10 1 read-only P11 Output Status 11 1 read-only P12 Output Status 12 1 read-only P13 Output Status 13 1 read-only P14 Output Status 14 1 read-only P15 Output Status 15 1 read-only P16 Output Status 16 1 read-only P17 Output Status 17 1 read-only P18 Output Status 18 1 read-only P19 Output Status 19 1 read-only P2 Output Status 2 1 read-only P20 Output Status 20 1 read-only P21 Output Status 21 1 read-only P22 Output Status 22 1 read-only P23 Output Status 23 1 read-only P24 Output Status 24 1 read-only P25 Output Status 25 1 read-only P26 Output Status 26 1 read-only P27 Output Status 27 1 read-only P28 Output Status 28 1 read-only P29 Output Status 29 1 read-only P3 Output Status 3 1 read-only P30 Output Status 30 1 read-only P31 Output Status 31 1 read-only P4 Output Status 4 1 read-only P5 Output Status 5 1 read-only P6 Output Status 6 1 read-only P7 Output Status 7 1 read-only P8 Output Status 8 1 read-only P9 Output Status 9 1 read-only OWDR Output Write Disable 0xA4 32 write-only n 0x0 0x0 P0 Output Write Disable 0 1 write-only P1 Output Write Disable 1 1 write-only P10 Output Write Disable 10 1 write-only P11 Output Write Disable 11 1 write-only P12 Output Write Disable 12 1 write-only P13 Output Write Disable 13 1 write-only P14 Output Write Disable 14 1 write-only P15 Output Write Disable 15 1 write-only P16 Output Write Disable 16 1 write-only P17 Output Write Disable 17 1 write-only P18 Output Write Disable 18 1 write-only P19 Output Write Disable 19 1 write-only P2 Output Write Disable 2 1 write-only P20 Output Write Disable 20 1 write-only P21 Output Write Disable 21 1 write-only P22 Output Write Disable 22 1 write-only P23 Output Write Disable 23 1 write-only P24 Output Write Disable 24 1 write-only P25 Output Write Disable 25 1 write-only P26 Output Write Disable 26 1 write-only P27 Output Write Disable 27 1 write-only P28 Output Write Disable 28 1 write-only P29 Output Write Disable 29 1 write-only P3 Output Write Disable 3 1 write-only P30 Output Write Disable 30 1 write-only P31 Output Write Disable 31 1 write-only P4 Output Write Disable 4 1 write-only P5 Output Write Disable 5 1 write-only P6 Output Write Disable 6 1 write-only P7 Output Write Disable 7 1 write-only P8 Output Write Disable 8 1 write-only P9 Output Write Disable 9 1 write-only OWER Output Write Enable 0xA0 32 write-only n 0x0 0x0 P0 Output Write Enable 0 1 write-only P1 Output Write Enable 1 1 write-only P10 Output Write Enable 10 1 write-only P11 Output Write Enable 11 1 write-only P12 Output Write Enable 12 1 write-only P13 Output Write Enable 13 1 write-only P14 Output Write Enable 14 1 write-only P15 Output Write Enable 15 1 write-only P16 Output Write Enable 16 1 write-only P17 Output Write Enable 17 1 write-only P18 Output Write Enable 18 1 write-only P19 Output Write Enable 19 1 write-only P2 Output Write Enable 2 1 write-only P20 Output Write Enable 20 1 write-only P21 Output Write Enable 21 1 write-only P22 Output Write Enable 22 1 write-only P23 Output Write Enable 23 1 write-only P24 Output Write Enable 24 1 write-only P25 Output Write Enable 25 1 write-only P26 Output Write Enable 26 1 write-only P27 Output Write Enable 27 1 write-only P28 Output Write Enable 28 1 write-only P29 Output Write Enable 29 1 write-only P3 Output Write Enable 3 1 write-only P30 Output Write Enable 30 1 write-only P31 Output Write Enable 31 1 write-only P4 Output Write Enable 4 1 write-only P5 Output Write Enable 5 1 write-only P6 Output Write Enable 6 1 write-only P7 Output Write Enable 7 1 write-only P8 Output Write Enable 8 1 write-only P9 Output Write Enable 9 1 write-only OWSR Output Write Status Register 0xA8 32 read-only n 0x0 0x0 P0 Output Write Status 0 1 read-only P1 Output Write Status 1 1 read-only P10 Output Write Status 10 1 read-only P11 Output Write Status 11 1 read-only P12 Output Write Status 12 1 read-only P13 Output Write Status 13 1 read-only P14 Output Write Status 14 1 read-only P15 Output Write Status 15 1 read-only P16 Output Write Status 16 1 read-only P17 Output Write Status 17 1 read-only P18 Output Write Status 18 1 read-only P19 Output Write Status 19 1 read-only P2 Output Write Status 2 1 read-only P20 Output Write Status 20 1 read-only P21 Output Write Status 21 1 read-only P22 Output Write Status 22 1 read-only P23 Output Write Status 23 1 read-only P24 Output Write Status 24 1 read-only P25 Output Write Status 25 1 read-only P26 Output Write Status 26 1 read-only P27 Output Write Status 27 1 read-only P28 Output Write Status 28 1 read-only P29 Output Write Status 29 1 read-only P3 Output Write Status 3 1 read-only P30 Output Write Status 30 1 read-only P31 Output Write Status 31 1 read-only P4 Output Write Status 4 1 read-only P5 Output Write Status 5 1 read-only P6 Output Write Status 6 1 read-only P7 Output Write Status 7 1 read-only P8 Output Write Status 8 1 read-only P9 Output Write Status 9 1 read-only PDR PIO Disable Register 0x4 32 write-only n 0x0 0x0 P0 PIO Disable 0 1 write-only P1 PIO Disable 1 1 write-only P10 PIO Disable 10 1 write-only P11 PIO Disable 11 1 write-only P12 PIO Disable 12 1 write-only P13 PIO Disable 13 1 write-only P14 PIO Disable 14 1 write-only P15 PIO Disable 15 1 write-only P16 PIO Disable 16 1 write-only P17 PIO Disable 17 1 write-only P18 PIO Disable 18 1 write-only P19 PIO Disable 19 1 write-only P2 PIO Disable 2 1 write-only P20 PIO Disable 20 1 write-only P21 PIO Disable 21 1 write-only P22 PIO Disable 22 1 write-only P23 PIO Disable 23 1 write-only P24 PIO Disable 24 1 write-only P25 PIO Disable 25 1 write-only P26 PIO Disable 26 1 write-only P27 PIO Disable 27 1 write-only P28 PIO Disable 28 1 write-only P29 PIO Disable 29 1 write-only P3 PIO Disable 3 1 write-only P30 PIO Disable 30 1 write-only P31 PIO Disable 31 1 write-only P4 PIO Disable 4 1 write-only P5 PIO Disable 5 1 write-only P6 PIO Disable 6 1 write-only P7 PIO Disable 7 1 write-only P8 PIO Disable 8 1 write-only P9 PIO Disable 9 1 write-only PDSR Pin Data Status Register 0x3C 32 read-only n 0x0 0x0 P0 Output Data Status 0 1 read-only P1 Output Data Status 1 1 read-only P10 Output Data Status 10 1 read-only P11 Output Data Status 11 1 read-only P12 Output Data Status 12 1 read-only P13 Output Data Status 13 1 read-only P14 Output Data Status 14 1 read-only P15 Output Data Status 15 1 read-only P16 Output Data Status 16 1 read-only P17 Output Data Status 17 1 read-only P18 Output Data Status 18 1 read-only P19 Output Data Status 19 1 read-only P2 Output Data Status 2 1 read-only P20 Output Data Status 20 1 read-only P21 Output Data Status 21 1 read-only P22 Output Data Status 22 1 read-only P23 Output Data Status 23 1 read-only P24 Output Data Status 24 1 read-only P25 Output Data Status 25 1 read-only P26 Output Data Status 26 1 read-only P27 Output Data Status 27 1 read-only P28 Output Data Status 28 1 read-only P29 Output Data Status 29 1 read-only P3 Output Data Status 3 1 read-only P30 Output Data Status 30 1 read-only P31 Output Data Status 31 1 read-only P4 Output Data Status 4 1 read-only P5 Output Data Status 5 1 read-only P6 Output Data Status 6 1 read-only P7 Output Data Status 7 1 read-only P8 Output Data Status 8 1 read-only P9 Output Data Status 9 1 read-only PER PIO Enable Register 0x0 32 write-only n 0x0 0x0 P0 PIO Enable 0 1 write-only P1 PIO Enable 1 1 write-only P10 PIO Enable 10 1 write-only P11 PIO Enable 11 1 write-only P12 PIO Enable 12 1 write-only P13 PIO Enable 13 1 write-only P14 PIO Enable 14 1 write-only P15 PIO Enable 15 1 write-only P16 PIO Enable 16 1 write-only P17 PIO Enable 17 1 write-only P18 PIO Enable 18 1 write-only P19 PIO Enable 19 1 write-only P2 PIO Enable 2 1 write-only P20 PIO Enable 20 1 write-only P21 PIO Enable 21 1 write-only P22 PIO Enable 22 1 write-only P23 PIO Enable 23 1 write-only P24 PIO Enable 24 1 write-only P25 PIO Enable 25 1 write-only P26 PIO Enable 26 1 write-only P27 PIO Enable 27 1 write-only P28 PIO Enable 28 1 write-only P29 PIO Enable 29 1 write-only P3 PIO Enable 3 1 write-only P30 PIO Enable 30 1 write-only P31 PIO Enable 31 1 write-only P4 PIO Enable 4 1 write-only P5 PIO Enable 5 1 write-only P6 PIO Enable 6 1 write-only P7 PIO Enable 7 1 write-only P8 PIO Enable 8 1 write-only P9 PIO Enable 9 1 write-only PPDDR Pad Pull-down Disable Register 0x90 32 write-only n 0x0 0x0 P0 Pull-Down Disable 0 1 write-only P1 Pull-Down Disable 1 1 write-only P10 Pull-Down Disable 10 1 write-only P11 Pull-Down Disable 11 1 write-only P12 Pull-Down Disable 12 1 write-only P13 Pull-Down Disable 13 1 write-only P14 Pull-Down Disable 14 1 write-only P15 Pull-Down Disable 15 1 write-only P16 Pull-Down Disable 16 1 write-only P17 Pull-Down Disable 17 1 write-only P18 Pull-Down Disable 18 1 write-only P19 Pull-Down Disable 19 1 write-only P2 Pull-Down Disable 2 1 write-only P20 Pull-Down Disable 20 1 write-only P21 Pull-Down Disable 21 1 write-only P22 Pull-Down Disable 22 1 write-only P23 Pull-Down Disable 23 1 write-only P24 Pull-Down Disable 24 1 write-only P25 Pull-Down Disable 25 1 write-only P26 Pull-Down Disable 26 1 write-only P27 Pull-Down Disable 27 1 write-only P28 Pull-Down Disable 28 1 write-only P29 Pull-Down Disable 29 1 write-only P3 Pull-Down Disable 3 1 write-only P30 Pull-Down Disable 30 1 write-only P31 Pull-Down Disable 31 1 write-only P4 Pull-Down Disable 4 1 write-only P5 Pull-Down Disable 5 1 write-only P6 Pull-Down Disable 6 1 write-only P7 Pull-Down Disable 7 1 write-only P8 Pull-Down Disable 8 1 write-only P9 Pull-Down Disable 9 1 write-only PPDER Pad Pull-down Enable Register 0x94 32 write-only n 0x0 0x0 P0 Pull-Down Enable 0 1 write-only P1 Pull-Down Enable 1 1 write-only P10 Pull-Down Enable 10 1 write-only P11 Pull-Down Enable 11 1 write-only P12 Pull-Down Enable 12 1 write-only P13 Pull-Down Enable 13 1 write-only P14 Pull-Down Enable 14 1 write-only P15 Pull-Down Enable 15 1 write-only P16 Pull-Down Enable 16 1 write-only P17 Pull-Down Enable 17 1 write-only P18 Pull-Down Enable 18 1 write-only P19 Pull-Down Enable 19 1 write-only P2 Pull-Down Enable 2 1 write-only P20 Pull-Down Enable 20 1 write-only P21 Pull-Down Enable 21 1 write-only P22 Pull-Down Enable 22 1 write-only P23 Pull-Down Enable 23 1 write-only P24 Pull-Down Enable 24 1 write-only P25 Pull-Down Enable 25 1 write-only P26 Pull-Down Enable 26 1 write-only P27 Pull-Down Enable 27 1 write-only P28 Pull-Down Enable 28 1 write-only P29 Pull-Down Enable 29 1 write-only P3 Pull-Down Enable 3 1 write-only P30 Pull-Down Enable 30 1 write-only P31 Pull-Down Enable 31 1 write-only P4 Pull-Down Enable 4 1 write-only P5 Pull-Down Enable 5 1 write-only P6 Pull-Down Enable 6 1 write-only P7 Pull-Down Enable 7 1 write-only P8 Pull-Down Enable 8 1 write-only P9 Pull-Down Enable 9 1 write-only PPDSR Pad Pull-down Status Register 0x98 32 read-only n 0x0 0x0 P0 Pull-Down Status 0 1 read-only P1 Pull-Down Status 1 1 read-only P10 Pull-Down Status 10 1 read-only P11 Pull-Down Status 11 1 read-only P12 Pull-Down Status 12 1 read-only P13 Pull-Down Status 13 1 read-only P14 Pull-Down Status 14 1 read-only P15 Pull-Down Status 15 1 read-only P16 Pull-Down Status 16 1 read-only P17 Pull-Down Status 17 1 read-only P18 Pull-Down Status 18 1 read-only P19 Pull-Down Status 19 1 read-only P2 Pull-Down Status 2 1 read-only P20 Pull-Down Status 20 1 read-only P21 Pull-Down Status 21 1 read-only P22 Pull-Down Status 22 1 read-only P23 Pull-Down Status 23 1 read-only P24 Pull-Down Status 24 1 read-only P25 Pull-Down Status 25 1 read-only P26 Pull-Down Status 26 1 read-only P27 Pull-Down Status 27 1 read-only P28 Pull-Down Status 28 1 read-only P29 Pull-Down Status 29 1 read-only P3 Pull-Down Status 3 1 read-only P30 Pull-Down Status 30 1 read-only P31 Pull-Down Status 31 1 read-only P4 Pull-Down Status 4 1 read-only P5 Pull-Down Status 5 1 read-only P6 Pull-Down Status 6 1 read-only P7 Pull-Down Status 7 1 read-only P8 Pull-Down Status 8 1 read-only P9 Pull-Down Status 9 1 read-only PSR PIO Status Register 0x8 32 read-only n 0x0 0x0 P0 PIO Status 0 1 read-only P1 PIO Status 1 1 read-only P10 PIO Status 10 1 read-only P11 PIO Status 11 1 read-only P12 PIO Status 12 1 read-only P13 PIO Status 13 1 read-only P14 PIO Status 14 1 read-only P15 PIO Status 15 1 read-only P16 PIO Status 16 1 read-only P17 PIO Status 17 1 read-only P18 PIO Status 18 1 read-only P19 PIO Status 19 1 read-only P2 PIO Status 2 1 read-only P20 PIO Status 20 1 read-only P21 PIO Status 21 1 read-only P22 PIO Status 22 1 read-only P23 PIO Status 23 1 read-only P24 PIO Status 24 1 read-only P25 PIO Status 25 1 read-only P26 PIO Status 26 1 read-only P27 PIO Status 27 1 read-only P28 PIO Status 28 1 read-only P29 PIO Status 29 1 read-only P3 PIO Status 3 1 read-only P30 PIO Status 30 1 read-only P31 PIO Status 31 1 read-only P4 PIO Status 4 1 read-only P5 PIO Status 5 1 read-only P6 PIO Status 6 1 read-only P7 PIO Status 7 1 read-only P8 PIO Status 8 1 read-only P9 PIO Status 9 1 read-only PUDR Pull-up Disable Register 0x60 32 write-only n 0x0 0x0 P0 Pull-Up Disable 0 1 write-only P1 Pull-Up Disable 1 1 write-only P10 Pull-Up Disable 10 1 write-only P11 Pull-Up Disable 11 1 write-only P12 Pull-Up Disable 12 1 write-only P13 Pull-Up Disable 13 1 write-only P14 Pull-Up Disable 14 1 write-only P15 Pull-Up Disable 15 1 write-only P16 Pull-Up Disable 16 1 write-only P17 Pull-Up Disable 17 1 write-only P18 Pull-Up Disable 18 1 write-only P19 Pull-Up Disable 19 1 write-only P2 Pull-Up Disable 2 1 write-only P20 Pull-Up Disable 20 1 write-only P21 Pull-Up Disable 21 1 write-only P22 Pull-Up Disable 22 1 write-only P23 Pull-Up Disable 23 1 write-only P24 Pull-Up Disable 24 1 write-only P25 Pull-Up Disable 25 1 write-only P26 Pull-Up Disable 26 1 write-only P27 Pull-Up Disable 27 1 write-only P28 Pull-Up Disable 28 1 write-only P29 Pull-Up Disable 29 1 write-only P3 Pull-Up Disable 3 1 write-only P30 Pull-Up Disable 30 1 write-only P31 Pull-Up Disable 31 1 write-only P4 Pull-Up Disable 4 1 write-only P5 Pull-Up Disable 5 1 write-only P6 Pull-Up Disable 6 1 write-only P7 Pull-Up Disable 7 1 write-only P8 Pull-Up Disable 8 1 write-only P9 Pull-Up Disable 9 1 write-only PUER Pull-up Enable Register 0x64 32 write-only n 0x0 0x0 P0 Pull-Up Enable 0 1 write-only P1 Pull-Up Enable 1 1 write-only P10 Pull-Up Enable 10 1 write-only P11 Pull-Up Enable 11 1 write-only P12 Pull-Up Enable 12 1 write-only P13 Pull-Up Enable 13 1 write-only P14 Pull-Up Enable 14 1 write-only P15 Pull-Up Enable 15 1 write-only P16 Pull-Up Enable 16 1 write-only P17 Pull-Up Enable 17 1 write-only P18 Pull-Up Enable 18 1 write-only P19 Pull-Up Enable 19 1 write-only P2 Pull-Up Enable 2 1 write-only P20 Pull-Up Enable 20 1 write-only P21 Pull-Up Enable 21 1 write-only P22 Pull-Up Enable 22 1 write-only P23 Pull-Up Enable 23 1 write-only P24 Pull-Up Enable 24 1 write-only P25 Pull-Up Enable 25 1 write-only P26 Pull-Up Enable 26 1 write-only P27 Pull-Up Enable 27 1 write-only P28 Pull-Up Enable 28 1 write-only P29 Pull-Up Enable 29 1 write-only P3 Pull-Up Enable 3 1 write-only P30 Pull-Up Enable 30 1 write-only P31 Pull-Up Enable 31 1 write-only P4 Pull-Up Enable 4 1 write-only P5 Pull-Up Enable 5 1 write-only P6 Pull-Up Enable 6 1 write-only P7 Pull-Up Enable 7 1 write-only P8 Pull-Up Enable 8 1 write-only P9 Pull-Up Enable 9 1 write-only PUSR Pad Pull-up Status Register 0x68 32 read-only n 0x0 0x0 P0 Pull-Up Status 0 1 read-only P1 Pull-Up Status 1 1 read-only P10 Pull-Up Status 10 1 read-only P11 Pull-Up Status 11 1 read-only P12 Pull-Up Status 12 1 read-only P13 Pull-Up Status 13 1 read-only P14 Pull-Up Status 14 1 read-only P15 Pull-Up Status 15 1 read-only P16 Pull-Up Status 16 1 read-only P17 Pull-Up Status 17 1 read-only P18 Pull-Up Status 18 1 read-only P19 Pull-Up Status 19 1 read-only P2 Pull-Up Status 2 1 read-only P20 Pull-Up Status 20 1 read-only P21 Pull-Up Status 21 1 read-only P22 Pull-Up Status 22 1 read-only P23 Pull-Up Status 23 1 read-only P24 Pull-Up Status 24 1 read-only P25 Pull-Up Status 25 1 read-only P26 Pull-Up Status 26 1 read-only P27 Pull-Up Status 27 1 read-only P28 Pull-Up Status 28 1 read-only P29 Pull-Up Status 29 1 read-only P3 Pull-Up Status 3 1 read-only P30 Pull-Up Status 30 1 read-only P31 Pull-Up Status 31 1 read-only P4 Pull-Up Status 4 1 read-only P5 Pull-Up Status 5 1 read-only P6 Pull-Up Status 6 1 read-only P7 Pull-Up Status 7 1 read-only P8 Pull-Up Status 8 1 read-only P9 Pull-Up Status 9 1 read-only REHLSR Rising Edge/ High-Level Select Register 0xD4 32 write-only n 0x0 0x0 P0 Rising Edge /High-Level Interrupt Selection 0 1 write-only P1 Rising Edge /High-Level Interrupt Selection 1 1 write-only P10 Rising Edge /High-Level Interrupt Selection 10 1 write-only P11 Rising Edge /High-Level Interrupt Selection 11 1 write-only P12 Rising Edge /High-Level Interrupt Selection 12 1 write-only P13 Rising Edge /High-Level Interrupt Selection 13 1 write-only P14 Rising Edge /High-Level Interrupt Selection 14 1 write-only P15 Rising Edge /High-Level Interrupt Selection 15 1 write-only P16 Rising Edge /High-Level Interrupt Selection 16 1 write-only P17 Rising Edge /High-Level Interrupt Selection 17 1 write-only P18 Rising Edge /High-Level Interrupt Selection 18 1 write-only P19 Rising Edge /High-Level Interrupt Selection 19 1 write-only P2 Rising Edge /High-Level Interrupt Selection 2 1 write-only P20 Rising Edge /High-Level Interrupt Selection 20 1 write-only P21 Rising Edge /High-Level Interrupt Selection 21 1 write-only P22 Rising Edge /High-Level Interrupt Selection 22 1 write-only P23 Rising Edge /High-Level Interrupt Selection 23 1 write-only P24 Rising Edge /High-Level Interrupt Selection 24 1 write-only P25 Rising Edge /High-Level Interrupt Selection 25 1 write-only P26 Rising Edge /High-Level Interrupt Selection 26 1 write-only P27 Rising Edge /High-Level Interrupt Selection 27 1 write-only P28 Rising Edge /High-Level Interrupt Selection 28 1 write-only P29 Rising Edge /High-Level Interrupt Selection 29 1 write-only P3 Rising Edge /High-Level Interrupt Selection 3 1 write-only P30 Rising Edge /High-Level Interrupt Selection 30 1 write-only P31 Rising Edge /High-Level Interrupt Selection 31 1 write-only P4 Rising Edge /High-Level Interrupt Selection 4 1 write-only P5 Rising Edge /High-Level Interrupt Selection 5 1 write-only P6 Rising Edge /High-Level Interrupt Selection 6 1 write-only P7 Rising Edge /High-Level Interrupt Selection 7 1 write-only P8 Rising Edge /High-Level Interrupt Selection 8 1 write-only P9 Rising Edge /High-Level Interrupt Selection 9 1 write-only SCDR Slow Clock Divider Debouncing Register 0x8C 32 read-write n 0x0 0x0 DIV Slow Clock Divider Selection for Debouncing 0 14 read-write SCHMITT Schmitt Trigger Register 0x100 32 read-write n 0x0 0x0 SCHMITT0 Schmitt Trigger Control 0 1 read-write SCHMITT1 Schmitt Trigger Control 1 1 read-write SCHMITT10 Schmitt Trigger Control 10 1 read-write SCHMITT11 Schmitt Trigger Control 11 1 read-write SCHMITT12 Schmitt Trigger Control 12 1 read-write SCHMITT13 Schmitt Trigger Control 13 1 read-write SCHMITT14 Schmitt Trigger Control 14 1 read-write SCHMITT15 Schmitt Trigger Control 15 1 read-write SCHMITT16 Schmitt Trigger Control 16 1 read-write SCHMITT17 Schmitt Trigger Control 17 1 read-write SCHMITT18 Schmitt Trigger Control 18 1 read-write SCHMITT19 Schmitt Trigger Control 19 1 read-write SCHMITT2 Schmitt Trigger Control 2 1 read-write SCHMITT20 Schmitt Trigger Control 20 1 read-write SCHMITT21 Schmitt Trigger Control 21 1 read-write SCHMITT22 Schmitt Trigger Control 22 1 read-write SCHMITT23 Schmitt Trigger Control 23 1 read-write SCHMITT24 Schmitt Trigger Control 24 1 read-write SCHMITT25 Schmitt Trigger Control 25 1 read-write SCHMITT26 Schmitt Trigger Control 26 1 read-write SCHMITT27 Schmitt Trigger Control 27 1 read-write SCHMITT28 Schmitt Trigger Control 28 1 read-write SCHMITT29 Schmitt Trigger Control 29 1 read-write SCHMITT3 Schmitt Trigger Control 3 1 read-write SCHMITT30 Schmitt Trigger Control 30 1 read-write SCHMITT31 Schmitt Trigger Control 31 1 read-write SCHMITT4 Schmitt Trigger Control 4 1 read-write SCHMITT5 Schmitt Trigger Control 5 1 read-write SCHMITT6 Schmitt Trigger Control 6 1 read-write SCHMITT7 Schmitt Trigger Control 7 1 read-write SCHMITT8 Schmitt Trigger Control 8 1 read-write SCHMITT9 Schmitt Trigger Control 9 1 read-write SODR Set Output Data Register 0x30 32 write-only n 0x0 0x0 P0 Set Output Data 0 1 write-only P1 Set Output Data 1 1 write-only P10 Set Output Data 10 1 write-only P11 Set Output Data 11 1 write-only P12 Set Output Data 12 1 write-only P13 Set Output Data 13 1 write-only P14 Set Output Data 14 1 write-only P15 Set Output Data 15 1 write-only P16 Set Output Data 16 1 write-only P17 Set Output Data 17 1 write-only P18 Set Output Data 18 1 write-only P19 Set Output Data 19 1 write-only P2 Set Output Data 2 1 write-only P20 Set Output Data 20 1 write-only P21 Set Output Data 21 1 write-only P22 Set Output Data 22 1 write-only P23 Set Output Data 23 1 write-only P24 Set Output Data 24 1 write-only P25 Set Output Data 25 1 write-only P26 Set Output Data 26 1 write-only P27 Set Output Data 27 1 write-only P28 Set Output Data 28 1 write-only P29 Set Output Data 29 1 write-only P3 Set Output Data 3 1 write-only P30 Set Output Data 30 1 write-only P31 Set Output Data 31 1 write-only P4 Set Output Data 4 1 write-only P5 Set Output Data 5 1 write-only P6 Set Output Data 6 1 write-only P7 Set Output Data 7 1 write-only P8 Set Output Data 8 1 write-only P9 Set Output Data 9 1 write-only WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key. 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 0x50494F WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only PIOB Parallel Input/Output Controller B PIO 0x0 0x0 0x200 registers n PIOB 12 ABCDSR0 Peripheral Select Register 0x70 32 read-write n P0 Peripheral Select 0 1 read-write P1 Peripheral Select 1 1 read-write P10 Peripheral Select 10 1 read-write P11 Peripheral Select 11 1 read-write P12 Peripheral Select 12 1 read-write P13 Peripheral Select 13 1 read-write P14 Peripheral Select 14 1 read-write P15 Peripheral Select 15 1 read-write P16 Peripheral Select 16 1 read-write P17 Peripheral Select 17 1 read-write P18 Peripheral Select 18 1 read-write P19 Peripheral Select 19 1 read-write P2 Peripheral Select 2 1 read-write P20 Peripheral Select 20 1 read-write P21 Peripheral Select 21 1 read-write P22 Peripheral Select 22 1 read-write P23 Peripheral Select 23 1 read-write P24 Peripheral Select 24 1 read-write P25 Peripheral Select 25 1 read-write P26 Peripheral Select 26 1 read-write P27 Peripheral Select 27 1 read-write P28 Peripheral Select 28 1 read-write P29 Peripheral Select 29 1 read-write P3 Peripheral Select 3 1 read-write P30 Peripheral Select 30 1 read-write P31 Peripheral Select 31 1 read-write P4 Peripheral Select 4 1 read-write P5 Peripheral Select 5 1 read-write P6 Peripheral Select 6 1 read-write P7 Peripheral Select 7 1 read-write P8 Peripheral Select 8 1 read-write P9 Peripheral Select 9 1 read-write ABCDSR1 Peripheral Select Register 0x74 32 read-write n P0 Peripheral Select 0 1 read-write P1 Peripheral Select 1 1 read-write P10 Peripheral Select 10 1 read-write P11 Peripheral Select 11 1 read-write P12 Peripheral Select 12 1 read-write P13 Peripheral Select 13 1 read-write P14 Peripheral Select 14 1 read-write P15 Peripheral Select 15 1 read-write P16 Peripheral Select 16 1 read-write P17 Peripheral Select 17 1 read-write P18 Peripheral Select 18 1 read-write P19 Peripheral Select 19 1 read-write P2 Peripheral Select 2 1 read-write P20 Peripheral Select 20 1 read-write P21 Peripheral Select 21 1 read-write P22 Peripheral Select 22 1 read-write P23 Peripheral Select 23 1 read-write P24 Peripheral Select 24 1 read-write P25 Peripheral Select 25 1 read-write P26 Peripheral Select 26 1 read-write P27 Peripheral Select 27 1 read-write P28 Peripheral Select 28 1 read-write P29 Peripheral Select 29 1 read-write P3 Peripheral Select 3 1 read-write P30 Peripheral Select 30 1 read-write P31 Peripheral Select 31 1 read-write P4 Peripheral Select 4 1 read-write P5 Peripheral Select 5 1 read-write P6 Peripheral Select 6 1 read-write P7 Peripheral Select 7 1 read-write P8 Peripheral Select 8 1 read-write P9 Peripheral Select 9 1 read-write ABCDSR[0] Peripheral Select Register 0xE0 32 read-write n 0x0 0x0 P0 Peripheral Select 0 1 read-write P1 Peripheral Select 1 1 read-write P10 Peripheral Select 10 1 read-write P11 Peripheral Select 11 1 read-write P12 Peripheral Select 12 1 read-write P13 Peripheral Select 13 1 read-write P14 Peripheral Select 14 1 read-write P15 Peripheral Select 15 1 read-write P16 Peripheral Select 16 1 read-write P17 Peripheral Select 17 1 read-write P18 Peripheral Select 18 1 read-write P19 Peripheral Select 19 1 read-write P2 Peripheral Select 2 1 read-write P20 Peripheral Select 20 1 read-write P21 Peripheral Select 21 1 read-write P22 Peripheral Select 22 1 read-write P23 Peripheral Select 23 1 read-write P24 Peripheral Select 24 1 read-write P25 Peripheral Select 25 1 read-write P26 Peripheral Select 26 1 read-write P27 Peripheral Select 27 1 read-write P28 Peripheral Select 28 1 read-write P29 Peripheral Select 29 1 read-write P3 Peripheral Select 3 1 read-write P30 Peripheral Select 30 1 read-write P31 Peripheral Select 31 1 read-write P4 Peripheral Select 4 1 read-write P5 Peripheral Select 5 1 read-write P6 Peripheral Select 6 1 read-write P7 Peripheral Select 7 1 read-write P8 Peripheral Select 8 1 read-write P9 Peripheral Select 9 1 read-write ABCDSR[1] Peripheral Select Register 0x154 32 read-write n 0x0 0x0 P0 Peripheral Select 0 1 read-write P1 Peripheral Select 1 1 read-write P10 Peripheral Select 10 1 read-write P11 Peripheral Select 11 1 read-write P12 Peripheral Select 12 1 read-write P13 Peripheral Select 13 1 read-write P14 Peripheral Select 14 1 read-write P15 Peripheral Select 15 1 read-write P16 Peripheral Select 16 1 read-write P17 Peripheral Select 17 1 read-write P18 Peripheral Select 18 1 read-write P19 Peripheral Select 19 1 read-write P2 Peripheral Select 2 1 read-write P20 Peripheral Select 20 1 read-write P21 Peripheral Select 21 1 read-write P22 Peripheral Select 22 1 read-write P23 Peripheral Select 23 1 read-write P24 Peripheral Select 24 1 read-write P25 Peripheral Select 25 1 read-write P26 Peripheral Select 26 1 read-write P27 Peripheral Select 27 1 read-write P28 Peripheral Select 28 1 read-write P29 Peripheral Select 29 1 read-write P3 Peripheral Select 3 1 read-write P30 Peripheral Select 30 1 read-write P31 Peripheral Select 31 1 read-write P4 Peripheral Select 4 1 read-write P5 Peripheral Select 5 1 read-write P6 Peripheral Select 6 1 read-write P7 Peripheral Select 7 1 read-write P8 Peripheral Select 8 1 read-write P9 Peripheral Select 9 1 read-write AIMDR Additional Interrupt Modes Disable Register 0xB4 32 write-only n 0x0 0x0 P0 Additional Interrupt Modes Disable 0 1 write-only P1 Additional Interrupt Modes Disable 1 1 write-only P10 Additional Interrupt Modes Disable 10 1 write-only P11 Additional Interrupt Modes Disable 11 1 write-only P12 Additional Interrupt Modes Disable 12 1 write-only P13 Additional Interrupt Modes Disable 13 1 write-only P14 Additional Interrupt Modes Disable 14 1 write-only P15 Additional Interrupt Modes Disable 15 1 write-only P16 Additional Interrupt Modes Disable 16 1 write-only P17 Additional Interrupt Modes Disable 17 1 write-only P18 Additional Interrupt Modes Disable 18 1 write-only P19 Additional Interrupt Modes Disable 19 1 write-only P2 Additional Interrupt Modes Disable 2 1 write-only P20 Additional Interrupt Modes Disable 20 1 write-only P21 Additional Interrupt Modes Disable 21 1 write-only P22 Additional Interrupt Modes Disable 22 1 write-only P23 Additional Interrupt Modes Disable 23 1 write-only P24 Additional Interrupt Modes Disable 24 1 write-only P25 Additional Interrupt Modes Disable 25 1 write-only P26 Additional Interrupt Modes Disable 26 1 write-only P27 Additional Interrupt Modes Disable 27 1 write-only P28 Additional Interrupt Modes Disable 28 1 write-only P29 Additional Interrupt Modes Disable 29 1 write-only P3 Additional Interrupt Modes Disable 3 1 write-only P30 Additional Interrupt Modes Disable 30 1 write-only P31 Additional Interrupt Modes Disable 31 1 write-only P4 Additional Interrupt Modes Disable 4 1 write-only P5 Additional Interrupt Modes Disable 5 1 write-only P6 Additional Interrupt Modes Disable 6 1 write-only P7 Additional Interrupt Modes Disable 7 1 write-only P8 Additional Interrupt Modes Disable 8 1 write-only P9 Additional Interrupt Modes Disable 9 1 write-only AIMER Additional Interrupt Modes Enable Register 0xB0 32 write-only n 0x0 0x0 P0 Additional Interrupt Modes Enable 0 1 write-only P1 Additional Interrupt Modes Enable 1 1 write-only P10 Additional Interrupt Modes Enable 10 1 write-only P11 Additional Interrupt Modes Enable 11 1 write-only P12 Additional Interrupt Modes Enable 12 1 write-only P13 Additional Interrupt Modes Enable 13 1 write-only P14 Additional Interrupt Modes Enable 14 1 write-only P15 Additional Interrupt Modes Enable 15 1 write-only P16 Additional Interrupt Modes Enable 16 1 write-only P17 Additional Interrupt Modes Enable 17 1 write-only P18 Additional Interrupt Modes Enable 18 1 write-only P19 Additional Interrupt Modes Enable 19 1 write-only P2 Additional Interrupt Modes Enable 2 1 write-only P20 Additional Interrupt Modes Enable 20 1 write-only P21 Additional Interrupt Modes Enable 21 1 write-only P22 Additional Interrupt Modes Enable 22 1 write-only P23 Additional Interrupt Modes Enable 23 1 write-only P24 Additional Interrupt Modes Enable 24 1 write-only P25 Additional Interrupt Modes Enable 25 1 write-only P26 Additional Interrupt Modes Enable 26 1 write-only P27 Additional Interrupt Modes Enable 27 1 write-only P28 Additional Interrupt Modes Enable 28 1 write-only P29 Additional Interrupt Modes Enable 29 1 write-only P3 Additional Interrupt Modes Enable 3 1 write-only P30 Additional Interrupt Modes Enable 30 1 write-only P31 Additional Interrupt Modes Enable 31 1 write-only P4 Additional Interrupt Modes Enable 4 1 write-only P5 Additional Interrupt Modes Enable 5 1 write-only P6 Additional Interrupt Modes Enable 6 1 write-only P7 Additional Interrupt Modes Enable 7 1 write-only P8 Additional Interrupt Modes Enable 8 1 write-only P9 Additional Interrupt Modes Enable 9 1 write-only AIMMR Additional Interrupt Modes Mask Register 0xB8 32 read-only n 0x0 0x0 P0 Peripheral CD Status 0 1 read-only P1 Peripheral CD Status 1 1 read-only P10 Peripheral CD Status 10 1 read-only P11 Peripheral CD Status 11 1 read-only P12 Peripheral CD Status 12 1 read-only P13 Peripheral CD Status 13 1 read-only P14 Peripheral CD Status 14 1 read-only P15 Peripheral CD Status 15 1 read-only P16 Peripheral CD Status 16 1 read-only P17 Peripheral CD Status 17 1 read-only P18 Peripheral CD Status 18 1 read-only P19 Peripheral CD Status 19 1 read-only P2 Peripheral CD Status 2 1 read-only P20 Peripheral CD Status 20 1 read-only P21 Peripheral CD Status 21 1 read-only P22 Peripheral CD Status 22 1 read-only P23 Peripheral CD Status 23 1 read-only P24 Peripheral CD Status 24 1 read-only P25 Peripheral CD Status 25 1 read-only P26 Peripheral CD Status 26 1 read-only P27 Peripheral CD Status 27 1 read-only P28 Peripheral CD Status 28 1 read-only P29 Peripheral CD Status 29 1 read-only P3 Peripheral CD Status 3 1 read-only P30 Peripheral CD Status 30 1 read-only P31 Peripheral CD Status 31 1 read-only P4 Peripheral CD Status 4 1 read-only P5 Peripheral CD Status 5 1 read-only P6 Peripheral CD Status 6 1 read-only P7 Peripheral CD Status 7 1 read-only P8 Peripheral CD Status 8 1 read-only P9 Peripheral CD Status 9 1 read-only CODR Clear Output Data Register 0x34 32 write-only n 0x0 0x0 P0 Clear Output Data 0 1 write-only P1 Clear Output Data 1 1 write-only P10 Clear Output Data 10 1 write-only P11 Clear Output Data 11 1 write-only P12 Clear Output Data 12 1 write-only P13 Clear Output Data 13 1 write-only P14 Clear Output Data 14 1 write-only P15 Clear Output Data 15 1 write-only P16 Clear Output Data 16 1 write-only P17 Clear Output Data 17 1 write-only P18 Clear Output Data 18 1 write-only P19 Clear Output Data 19 1 write-only P2 Clear Output Data 2 1 write-only P20 Clear Output Data 20 1 write-only P21 Clear Output Data 21 1 write-only P22 Clear Output Data 22 1 write-only P23 Clear Output Data 23 1 write-only P24 Clear Output Data 24 1 write-only P25 Clear Output Data 25 1 write-only P26 Clear Output Data 26 1 write-only P27 Clear Output Data 27 1 write-only P28 Clear Output Data 28 1 write-only P29 Clear Output Data 29 1 write-only P3 Clear Output Data 3 1 write-only P30 Clear Output Data 30 1 write-only P31 Clear Output Data 31 1 write-only P4 Clear Output Data 4 1 write-only P5 Clear Output Data 5 1 write-only P6 Clear Output Data 6 1 write-only P7 Clear Output Data 7 1 write-only P8 Clear Output Data 8 1 write-only P9 Clear Output Data 9 1 write-only ELSR Edge/Level Status Register 0xC8 32 read-only n 0x0 0x0 P0 Edge/Level Interrupt Source Selection 0 1 read-only P1 Edge/Level Interrupt Source Selection 1 1 read-only P10 Edge/Level Interrupt Source Selection 10 1 read-only P11 Edge/Level Interrupt Source Selection 11 1 read-only P12 Edge/Level Interrupt Source Selection 12 1 read-only P13 Edge/Level Interrupt Source Selection 13 1 read-only P14 Edge/Level Interrupt Source Selection 14 1 read-only P15 Edge/Level Interrupt Source Selection 15 1 read-only P16 Edge/Level Interrupt Source Selection 16 1 read-only P17 Edge/Level Interrupt Source Selection 17 1 read-only P18 Edge/Level Interrupt Source Selection 18 1 read-only P19 Edge/Level Interrupt Source Selection 19 1 read-only P2 Edge/Level Interrupt Source Selection 2 1 read-only P20 Edge/Level Interrupt Source Selection 20 1 read-only P21 Edge/Level Interrupt Source Selection 21 1 read-only P22 Edge/Level Interrupt Source Selection 22 1 read-only P23 Edge/Level Interrupt Source Selection 23 1 read-only P24 Edge/Level Interrupt Source Selection 24 1 read-only P25 Edge/Level Interrupt Source Selection 25 1 read-only P26 Edge/Level Interrupt Source Selection 26 1 read-only P27 Edge/Level Interrupt Source Selection 27 1 read-only P28 Edge/Level Interrupt Source Selection 28 1 read-only P29 Edge/Level Interrupt Source Selection 29 1 read-only P3 Edge/Level Interrupt Source Selection 3 1 read-only P30 Edge/Level Interrupt Source Selection 30 1 read-only P31 Edge/Level Interrupt Source Selection 31 1 read-only P4 Edge/Level Interrupt Source Selection 4 1 read-only P5 Edge/Level Interrupt Source Selection 5 1 read-only P6 Edge/Level Interrupt Source Selection 6 1 read-only P7 Edge/Level Interrupt Source Selection 7 1 read-only P8 Edge/Level Interrupt Source Selection 8 1 read-only P9 Edge/Level Interrupt Source Selection 9 1 read-only ESR Edge Select Register 0xC0 32 write-only n 0x0 0x0 P0 Edge Interrupt Selection 0 1 write-only P1 Edge Interrupt Selection 1 1 write-only P10 Edge Interrupt Selection 10 1 write-only P11 Edge Interrupt Selection 11 1 write-only P12 Edge Interrupt Selection 12 1 write-only P13 Edge Interrupt Selection 13 1 write-only P14 Edge Interrupt Selection 14 1 write-only P15 Edge Interrupt Selection 15 1 write-only P16 Edge Interrupt Selection 16 1 write-only P17 Edge Interrupt Selection 17 1 write-only P18 Edge Interrupt Selection 18 1 write-only P19 Edge Interrupt Selection 19 1 write-only P2 Edge Interrupt Selection 2 1 write-only P20 Edge Interrupt Selection 20 1 write-only P21 Edge Interrupt Selection 21 1 write-only P22 Edge Interrupt Selection 22 1 write-only P23 Edge Interrupt Selection 23 1 write-only P24 Edge Interrupt Selection 24 1 write-only P25 Edge Interrupt Selection 25 1 write-only P26 Edge Interrupt Selection 26 1 write-only P27 Edge Interrupt Selection 27 1 write-only P28 Edge Interrupt Selection 28 1 write-only P29 Edge Interrupt Selection 29 1 write-only P3 Edge Interrupt Selection 3 1 write-only P30 Edge Interrupt Selection 30 1 write-only P31 Edge Interrupt Selection 31 1 write-only P4 Edge Interrupt Selection 4 1 write-only P5 Edge Interrupt Selection 5 1 write-only P6 Edge Interrupt Selection 6 1 write-only P7 Edge Interrupt Selection 7 1 write-only P8 Edge Interrupt Selection 8 1 write-only P9 Edge Interrupt Selection 9 1 write-only FELLSR Falling Edge/Low-Level Select Register 0xD0 32 write-only n 0x0 0x0 P0 Falling Edge/Low-Level Interrupt Selection 0 1 write-only P1 Falling Edge/Low-Level Interrupt Selection 1 1 write-only P10 Falling Edge/Low-Level Interrupt Selection 10 1 write-only P11 Falling Edge/Low-Level Interrupt Selection 11 1 write-only P12 Falling Edge/Low-Level Interrupt Selection 12 1 write-only P13 Falling Edge/Low-Level Interrupt Selection 13 1 write-only P14 Falling Edge/Low-Level Interrupt Selection 14 1 write-only P15 Falling Edge/Low-Level Interrupt Selection 15 1 write-only P16 Falling Edge/Low-Level Interrupt Selection 16 1 write-only P17 Falling Edge/Low-Level Interrupt Selection 17 1 write-only P18 Falling Edge/Low-Level Interrupt Selection 18 1 write-only P19 Falling Edge/Low-Level Interrupt Selection 19 1 write-only P2 Falling Edge/Low-Level Interrupt Selection 2 1 write-only P20 Falling Edge/Low-Level Interrupt Selection 20 1 write-only P21 Falling Edge/Low-Level Interrupt Selection 21 1 write-only P22 Falling Edge/Low-Level Interrupt Selection 22 1 write-only P23 Falling Edge/Low-Level Interrupt Selection 23 1 write-only P24 Falling Edge/Low-Level Interrupt Selection 24 1 write-only P25 Falling Edge/Low-Level Interrupt Selection 25 1 write-only P26 Falling Edge/Low-Level Interrupt Selection 26 1 write-only P27 Falling Edge/Low-Level Interrupt Selection 27 1 write-only P28 Falling Edge/Low-Level Interrupt Selection 28 1 write-only P29 Falling Edge/Low-Level Interrupt Selection 29 1 write-only P3 Falling Edge/Low-Level Interrupt Selection 3 1 write-only P30 Falling Edge/Low-Level Interrupt Selection 30 1 write-only P31 Falling Edge/Low-Level Interrupt Selection 31 1 write-only P4 Falling Edge/Low-Level Interrupt Selection 4 1 write-only P5 Falling Edge/Low-Level Interrupt Selection 5 1 write-only P6 Falling Edge/Low-Level Interrupt Selection 6 1 write-only P7 Falling Edge/Low-Level Interrupt Selection 7 1 write-only P8 Falling Edge/Low-Level Interrupt Selection 8 1 write-only P9 Falling Edge/Low-Level Interrupt Selection 9 1 write-only FRLHSR Fall/Rise - Low/High Status Register 0xD8 32 read-only n 0x0 0x0 P0 Edge /Level Interrupt Source Selection 0 1 read-only P1 Edge /Level Interrupt Source Selection 1 1 read-only P10 Edge /Level Interrupt Source Selection 10 1 read-only P11 Edge /Level Interrupt Source Selection 11 1 read-only P12 Edge /Level Interrupt Source Selection 12 1 read-only P13 Edge /Level Interrupt Source Selection 13 1 read-only P14 Edge /Level Interrupt Source Selection 14 1 read-only P15 Edge /Level Interrupt Source Selection 15 1 read-only P16 Edge /Level Interrupt Source Selection 16 1 read-only P17 Edge /Level Interrupt Source Selection 17 1 read-only P18 Edge /Level Interrupt Source Selection 18 1 read-only P19 Edge /Level Interrupt Source Selection 19 1 read-only P2 Edge /Level Interrupt Source Selection 2 1 read-only P20 Edge /Level Interrupt Source Selection 20 1 read-only P21 Edge /Level Interrupt Source Selection 21 1 read-only P22 Edge /Level Interrupt Source Selection 22 1 read-only P23 Edge /Level Interrupt Source Selection 23 1 read-only P24 Edge /Level Interrupt Source Selection 24 1 read-only P25 Edge /Level Interrupt Source Selection 25 1 read-only P26 Edge /Level Interrupt Source Selection 26 1 read-only P27 Edge /Level Interrupt Source Selection 27 1 read-only P28 Edge /Level Interrupt Source Selection 28 1 read-only P29 Edge /Level Interrupt Source Selection 29 1 read-only P3 Edge /Level Interrupt Source Selection 3 1 read-only P30 Edge /Level Interrupt Source Selection 30 1 read-only P31 Edge /Level Interrupt Source Selection 31 1 read-only P4 Edge /Level Interrupt Source Selection 4 1 read-only P5 Edge /Level Interrupt Source Selection 5 1 read-only P6 Edge /Level Interrupt Source Selection 6 1 read-only P7 Edge /Level Interrupt Source Selection 7 1 read-only P8 Edge /Level Interrupt Source Selection 8 1 read-only P9 Edge /Level Interrupt Source Selection 9 1 read-only IDR Interrupt Disable Register 0x44 32 write-only n 0x0 0x0 P0 Input Change Interrupt Disable 0 1 write-only P1 Input Change Interrupt Disable 1 1 write-only P10 Input Change Interrupt Disable 10 1 write-only P11 Input Change Interrupt Disable 11 1 write-only P12 Input Change Interrupt Disable 12 1 write-only P13 Input Change Interrupt Disable 13 1 write-only P14 Input Change Interrupt Disable 14 1 write-only P15 Input Change Interrupt Disable 15 1 write-only P16 Input Change Interrupt Disable 16 1 write-only P17 Input Change Interrupt Disable 17 1 write-only P18 Input Change Interrupt Disable 18 1 write-only P19 Input Change Interrupt Disable 19 1 write-only P2 Input Change Interrupt Disable 2 1 write-only P20 Input Change Interrupt Disable 20 1 write-only P21 Input Change Interrupt Disable 21 1 write-only P22 Input Change Interrupt Disable 22 1 write-only P23 Input Change Interrupt Disable 23 1 write-only P24 Input Change Interrupt Disable 24 1 write-only P25 Input Change Interrupt Disable 25 1 write-only P26 Input Change Interrupt Disable 26 1 write-only P27 Input Change Interrupt Disable 27 1 write-only P28 Input Change Interrupt Disable 28 1 write-only P29 Input Change Interrupt Disable 29 1 write-only P3 Input Change Interrupt Disable 3 1 write-only P30 Input Change Interrupt Disable 30 1 write-only P31 Input Change Interrupt Disable 31 1 write-only P4 Input Change Interrupt Disable 4 1 write-only P5 Input Change Interrupt Disable 5 1 write-only P6 Input Change Interrupt Disable 6 1 write-only P7 Input Change Interrupt Disable 7 1 write-only P8 Input Change Interrupt Disable 8 1 write-only P9 Input Change Interrupt Disable 9 1 write-only IER Interrupt Enable Register 0x40 32 write-only n 0x0 0x0 P0 Input Change Interrupt Enable 0 1 write-only P1 Input Change Interrupt Enable 1 1 write-only P10 Input Change Interrupt Enable 10 1 write-only P11 Input Change Interrupt Enable 11 1 write-only P12 Input Change Interrupt Enable 12 1 write-only P13 Input Change Interrupt Enable 13 1 write-only P14 Input Change Interrupt Enable 14 1 write-only P15 Input Change Interrupt Enable 15 1 write-only P16 Input Change Interrupt Enable 16 1 write-only P17 Input Change Interrupt Enable 17 1 write-only P18 Input Change Interrupt Enable 18 1 write-only P19 Input Change Interrupt Enable 19 1 write-only P2 Input Change Interrupt Enable 2 1 write-only P20 Input Change Interrupt Enable 20 1 write-only P21 Input Change Interrupt Enable 21 1 write-only P22 Input Change Interrupt Enable 22 1 write-only P23 Input Change Interrupt Enable 23 1 write-only P24 Input Change Interrupt Enable 24 1 write-only P25 Input Change Interrupt Enable 25 1 write-only P26 Input Change Interrupt Enable 26 1 write-only P27 Input Change Interrupt Enable 27 1 write-only P28 Input Change Interrupt Enable 28 1 write-only P29 Input Change Interrupt Enable 29 1 write-only P3 Input Change Interrupt Enable 3 1 write-only P30 Input Change Interrupt Enable 30 1 write-only P31 Input Change Interrupt Enable 31 1 write-only P4 Input Change Interrupt Enable 4 1 write-only P5 Input Change Interrupt Enable 5 1 write-only P6 Input Change Interrupt Enable 6 1 write-only P7 Input Change Interrupt Enable 7 1 write-only P8 Input Change Interrupt Enable 8 1 write-only P9 Input Change Interrupt Enable 9 1 write-only IFDR Glitch Input Filter Disable Register 0x24 32 write-only n 0x0 0x0 P0 Input Filter Disable 0 1 write-only P1 Input Filter Disable 1 1 write-only P10 Input Filter Disable 10 1 write-only P11 Input Filter Disable 11 1 write-only P12 Input Filter Disable 12 1 write-only P13 Input Filter Disable 13 1 write-only P14 Input Filter Disable 14 1 write-only P15 Input Filter Disable 15 1 write-only P16 Input Filter Disable 16 1 write-only P17 Input Filter Disable 17 1 write-only P18 Input Filter Disable 18 1 write-only P19 Input Filter Disable 19 1 write-only P2 Input Filter Disable 2 1 write-only P20 Input Filter Disable 20 1 write-only P21 Input Filter Disable 21 1 write-only P22 Input Filter Disable 22 1 write-only P23 Input Filter Disable 23 1 write-only P24 Input Filter Disable 24 1 write-only P25 Input Filter Disable 25 1 write-only P26 Input Filter Disable 26 1 write-only P27 Input Filter Disable 27 1 write-only P28 Input Filter Disable 28 1 write-only P29 Input Filter Disable 29 1 write-only P3 Input Filter Disable 3 1 write-only P30 Input Filter Disable 30 1 write-only P31 Input Filter Disable 31 1 write-only P4 Input Filter Disable 4 1 write-only P5 Input Filter Disable 5 1 write-only P6 Input Filter Disable 6 1 write-only P7 Input Filter Disable 7 1 write-only P8 Input Filter Disable 8 1 write-only P9 Input Filter Disable 9 1 write-only IFER Glitch Input Filter Enable Register 0x20 32 write-only n 0x0 0x0 P0 Input Filter Enable 0 1 write-only P1 Input Filter Enable 1 1 write-only P10 Input Filter Enable 10 1 write-only P11 Input Filter Enable 11 1 write-only P12 Input Filter Enable 12 1 write-only P13 Input Filter Enable 13 1 write-only P14 Input Filter Enable 14 1 write-only P15 Input Filter Enable 15 1 write-only P16 Input Filter Enable 16 1 write-only P17 Input Filter Enable 17 1 write-only P18 Input Filter Enable 18 1 write-only P19 Input Filter Enable 19 1 write-only P2 Input Filter Enable 2 1 write-only P20 Input Filter Enable 20 1 write-only P21 Input Filter Enable 21 1 write-only P22 Input Filter Enable 22 1 write-only P23 Input Filter Enable 23 1 write-only P24 Input Filter Enable 24 1 write-only P25 Input Filter Enable 25 1 write-only P26 Input Filter Enable 26 1 write-only P27 Input Filter Enable 27 1 write-only P28 Input Filter Enable 28 1 write-only P29 Input Filter Enable 29 1 write-only P3 Input Filter Enable 3 1 write-only P30 Input Filter Enable 30 1 write-only P31 Input Filter Enable 31 1 write-only P4 Input Filter Enable 4 1 write-only P5 Input Filter Enable 5 1 write-only P6 Input Filter Enable 6 1 write-only P7 Input Filter Enable 7 1 write-only P8 Input Filter Enable 8 1 write-only P9 Input Filter Enable 9 1 write-only IFSCDR Input Filter Slow Clock Disable Register 0x80 32 write-only n 0x0 0x0 P0 PIO Clock Glitch Filtering Select 0 1 write-only P1 PIO Clock Glitch Filtering Select 1 1 write-only P10 PIO Clock Glitch Filtering Select 10 1 write-only P11 PIO Clock Glitch Filtering Select 11 1 write-only P12 PIO Clock Glitch Filtering Select 12 1 write-only P13 PIO Clock Glitch Filtering Select 13 1 write-only P14 PIO Clock Glitch Filtering Select 14 1 write-only P15 PIO Clock Glitch Filtering Select 15 1 write-only P16 PIO Clock Glitch Filtering Select 16 1 write-only P17 PIO Clock Glitch Filtering Select 17 1 write-only P18 PIO Clock Glitch Filtering Select 18 1 write-only P19 PIO Clock Glitch Filtering Select 19 1 write-only P2 PIO Clock Glitch Filtering Select 2 1 write-only P20 PIO Clock Glitch Filtering Select 20 1 write-only P21 PIO Clock Glitch Filtering Select 21 1 write-only P22 PIO Clock Glitch Filtering Select 22 1 write-only P23 PIO Clock Glitch Filtering Select 23 1 write-only P24 PIO Clock Glitch Filtering Select 24 1 write-only P25 PIO Clock Glitch Filtering Select 25 1 write-only P26 PIO Clock Glitch Filtering Select 26 1 write-only P27 PIO Clock Glitch Filtering Select 27 1 write-only P28 PIO Clock Glitch Filtering Select 28 1 write-only P29 PIO Clock Glitch Filtering Select 29 1 write-only P3 PIO Clock Glitch Filtering Select 3 1 write-only P30 PIO Clock Glitch Filtering Select 30 1 write-only P31 PIO Clock Glitch Filtering Select 31 1 write-only P4 PIO Clock Glitch Filtering Select 4 1 write-only P5 PIO Clock Glitch Filtering Select 5 1 write-only P6 PIO Clock Glitch Filtering Select 6 1 write-only P7 PIO Clock Glitch Filtering Select 7 1 write-only P8 PIO Clock Glitch Filtering Select 8 1 write-only P9 PIO Clock Glitch Filtering Select 9 1 write-only IFSCER Input Filter Slow Clock Enable Register 0x84 32 write-only n 0x0 0x0 P0 Debouncing Filtering Select 0 1 write-only P1 Debouncing Filtering Select 1 1 write-only P10 Debouncing Filtering Select 10 1 write-only P11 Debouncing Filtering Select 11 1 write-only P12 Debouncing Filtering Select 12 1 write-only P13 Debouncing Filtering Select 13 1 write-only P14 Debouncing Filtering Select 14 1 write-only P15 Debouncing Filtering Select 15 1 write-only P16 Debouncing Filtering Select 16 1 write-only P17 Debouncing Filtering Select 17 1 write-only P18 Debouncing Filtering Select 18 1 write-only P19 Debouncing Filtering Select 19 1 write-only P2 Debouncing Filtering Select 2 1 write-only P20 Debouncing Filtering Select 20 1 write-only P21 Debouncing Filtering Select 21 1 write-only P22 Debouncing Filtering Select 22 1 write-only P23 Debouncing Filtering Select 23 1 write-only P24 Debouncing Filtering Select 24 1 write-only P25 Debouncing Filtering Select 25 1 write-only P26 Debouncing Filtering Select 26 1 write-only P27 Debouncing Filtering Select 27 1 write-only P28 Debouncing Filtering Select 28 1 write-only P29 Debouncing Filtering Select 29 1 write-only P3 Debouncing Filtering Select 3 1 write-only P30 Debouncing Filtering Select 30 1 write-only P31 Debouncing Filtering Select 31 1 write-only P4 Debouncing Filtering Select 4 1 write-only P5 Debouncing Filtering Select 5 1 write-only P6 Debouncing Filtering Select 6 1 write-only P7 Debouncing Filtering Select 7 1 write-only P8 Debouncing Filtering Select 8 1 write-only P9 Debouncing Filtering Select 9 1 write-only IFSCSR Input Filter Slow Clock Status Register 0x88 32 read-only n 0x0 0x0 P0 Glitch or Debouncing Filter Selection Status 0 1 read-only P1 Glitch or Debouncing Filter Selection Status 1 1 read-only P10 Glitch or Debouncing Filter Selection Status 10 1 read-only P11 Glitch or Debouncing Filter Selection Status 11 1 read-only P12 Glitch or Debouncing Filter Selection Status 12 1 read-only P13 Glitch or Debouncing Filter Selection Status 13 1 read-only P14 Glitch or Debouncing Filter Selection Status 14 1 read-only P15 Glitch or Debouncing Filter Selection Status 15 1 read-only P16 Glitch or Debouncing Filter Selection Status 16 1 read-only P17 Glitch or Debouncing Filter Selection Status 17 1 read-only P18 Glitch or Debouncing Filter Selection Status 18 1 read-only P19 Glitch or Debouncing Filter Selection Status 19 1 read-only P2 Glitch or Debouncing Filter Selection Status 2 1 read-only P20 Glitch or Debouncing Filter Selection Status 20 1 read-only P21 Glitch or Debouncing Filter Selection Status 21 1 read-only P22 Glitch or Debouncing Filter Selection Status 22 1 read-only P23 Glitch or Debouncing Filter Selection Status 23 1 read-only P24 Glitch or Debouncing Filter Selection Status 24 1 read-only P25 Glitch or Debouncing Filter Selection Status 25 1 read-only P26 Glitch or Debouncing Filter Selection Status 26 1 read-only P27 Glitch or Debouncing Filter Selection Status 27 1 read-only P28 Glitch or Debouncing Filter Selection Status 28 1 read-only P29 Glitch or Debouncing Filter Selection Status 29 1 read-only P3 Glitch or Debouncing Filter Selection Status 3 1 read-only P30 Glitch or Debouncing Filter Selection Status 30 1 read-only P31 Glitch or Debouncing Filter Selection Status 31 1 read-only P4 Glitch or Debouncing Filter Selection Status 4 1 read-only P5 Glitch or Debouncing Filter Selection Status 5 1 read-only P6 Glitch or Debouncing Filter Selection Status 6 1 read-only P7 Glitch or Debouncing Filter Selection Status 7 1 read-only P8 Glitch or Debouncing Filter Selection Status 8 1 read-only P9 Glitch or Debouncing Filter Selection Status 9 1 read-only IFSR Glitch Input Filter Status Register 0x28 32 read-only n 0x0 0x0 P0 Input Filer Status 0 1 read-only P1 Input Filer Status 1 1 read-only P10 Input Filer Status 10 1 read-only P11 Input Filer Status 11 1 read-only P12 Input Filer Status 12 1 read-only P13 Input Filer Status 13 1 read-only P14 Input Filer Status 14 1 read-only P15 Input Filer Status 15 1 read-only P16 Input Filer Status 16 1 read-only P17 Input Filer Status 17 1 read-only P18 Input Filer Status 18 1 read-only P19 Input Filer Status 19 1 read-only P2 Input Filer Status 2 1 read-only P20 Input Filer Status 20 1 read-only P21 Input Filer Status 21 1 read-only P22 Input Filer Status 22 1 read-only P23 Input Filer Status 23 1 read-only P24 Input Filer Status 24 1 read-only P25 Input Filer Status 25 1 read-only P26 Input Filer Status 26 1 read-only P27 Input Filer Status 27 1 read-only P28 Input Filer Status 28 1 read-only P29 Input Filer Status 29 1 read-only P3 Input Filer Status 3 1 read-only P30 Input Filer Status 30 1 read-only P31 Input Filer Status 31 1 read-only P4 Input Filer Status 4 1 read-only P5 Input Filer Status 5 1 read-only P6 Input Filer Status 6 1 read-only P7 Input Filer Status 7 1 read-only P8 Input Filer Status 8 1 read-only P9 Input Filer Status 9 1 read-only IMR Interrupt Mask Register 0x48 32 read-only n 0x0 0x0 P0 Input Change Interrupt Mask 0 1 read-only P1 Input Change Interrupt Mask 1 1 read-only P10 Input Change Interrupt Mask 10 1 read-only P11 Input Change Interrupt Mask 11 1 read-only P12 Input Change Interrupt Mask 12 1 read-only P13 Input Change Interrupt Mask 13 1 read-only P14 Input Change Interrupt Mask 14 1 read-only P15 Input Change Interrupt Mask 15 1 read-only P16 Input Change Interrupt Mask 16 1 read-only P17 Input Change Interrupt Mask 17 1 read-only P18 Input Change Interrupt Mask 18 1 read-only P19 Input Change Interrupt Mask 19 1 read-only P2 Input Change Interrupt Mask 2 1 read-only P20 Input Change Interrupt Mask 20 1 read-only P21 Input Change Interrupt Mask 21 1 read-only P22 Input Change Interrupt Mask 22 1 read-only P23 Input Change Interrupt Mask 23 1 read-only P24 Input Change Interrupt Mask 24 1 read-only P25 Input Change Interrupt Mask 25 1 read-only P26 Input Change Interrupt Mask 26 1 read-only P27 Input Change Interrupt Mask 27 1 read-only P28 Input Change Interrupt Mask 28 1 read-only P29 Input Change Interrupt Mask 29 1 read-only P3 Input Change Interrupt Mask 3 1 read-only P30 Input Change Interrupt Mask 30 1 read-only P31 Input Change Interrupt Mask 31 1 read-only P4 Input Change Interrupt Mask 4 1 read-only P5 Input Change Interrupt Mask 5 1 read-only P6 Input Change Interrupt Mask 6 1 read-only P7 Input Change Interrupt Mask 7 1 read-only P8 Input Change Interrupt Mask 8 1 read-only P9 Input Change Interrupt Mask 9 1 read-only ISR Interrupt Status Register 0x4C 32 read-only n 0x0 0x0 P0 Input Change Interrupt Status 0 1 read-only P1 Input Change Interrupt Status 1 1 read-only P10 Input Change Interrupt Status 10 1 read-only P11 Input Change Interrupt Status 11 1 read-only P12 Input Change Interrupt Status 12 1 read-only P13 Input Change Interrupt Status 13 1 read-only P14 Input Change Interrupt Status 14 1 read-only P15 Input Change Interrupt Status 15 1 read-only P16 Input Change Interrupt Status 16 1 read-only P17 Input Change Interrupt Status 17 1 read-only P18 Input Change Interrupt Status 18 1 read-only P19 Input Change Interrupt Status 19 1 read-only P2 Input Change Interrupt Status 2 1 read-only P20 Input Change Interrupt Status 20 1 read-only P21 Input Change Interrupt Status 21 1 read-only P22 Input Change Interrupt Status 22 1 read-only P23 Input Change Interrupt Status 23 1 read-only P24 Input Change Interrupt Status 24 1 read-only P25 Input Change Interrupt Status 25 1 read-only P26 Input Change Interrupt Status 26 1 read-only P27 Input Change Interrupt Status 27 1 read-only P28 Input Change Interrupt Status 28 1 read-only P29 Input Change Interrupt Status 29 1 read-only P3 Input Change Interrupt Status 3 1 read-only P30 Input Change Interrupt Status 30 1 read-only P31 Input Change Interrupt Status 31 1 read-only P4 Input Change Interrupt Status 4 1 read-only P5 Input Change Interrupt Status 5 1 read-only P6 Input Change Interrupt Status 6 1 read-only P7 Input Change Interrupt Status 7 1 read-only P8 Input Change Interrupt Status 8 1 read-only P9 Input Change Interrupt Status 9 1 read-only LSR Level Select Register 0xC4 32 write-only n 0x0 0x0 P0 Level Interrupt Selection 0 1 write-only P1 Level Interrupt Selection 1 1 write-only P10 Level Interrupt Selection 10 1 write-only P11 Level Interrupt Selection 11 1 write-only P12 Level Interrupt Selection 12 1 write-only P13 Level Interrupt Selection 13 1 write-only P14 Level Interrupt Selection 14 1 write-only P15 Level Interrupt Selection 15 1 write-only P16 Level Interrupt Selection 16 1 write-only P17 Level Interrupt Selection 17 1 write-only P18 Level Interrupt Selection 18 1 write-only P19 Level Interrupt Selection 19 1 write-only P2 Level Interrupt Selection 2 1 write-only P20 Level Interrupt Selection 20 1 write-only P21 Level Interrupt Selection 21 1 write-only P22 Level Interrupt Selection 22 1 write-only P23 Level Interrupt Selection 23 1 write-only P24 Level Interrupt Selection 24 1 write-only P25 Level Interrupt Selection 25 1 write-only P26 Level Interrupt Selection 26 1 write-only P27 Level Interrupt Selection 27 1 write-only P28 Level Interrupt Selection 28 1 write-only P29 Level Interrupt Selection 29 1 write-only P3 Level Interrupt Selection 3 1 write-only P30 Level Interrupt Selection 30 1 write-only P31 Level Interrupt Selection 31 1 write-only P4 Level Interrupt Selection 4 1 write-only P5 Level Interrupt Selection 5 1 write-only P6 Level Interrupt Selection 6 1 write-only P7 Level Interrupt Selection 7 1 write-only P8 Level Interrupt Selection 8 1 write-only P9 Level Interrupt Selection 9 1 write-only MDDR Multi-driver Disable Register 0x54 32 write-only n 0x0 0x0 P0 Multi-Drive Disable 0 1 write-only P1 Multi-Drive Disable 1 1 write-only P10 Multi-Drive Disable 10 1 write-only P11 Multi-Drive Disable 11 1 write-only P12 Multi-Drive Disable 12 1 write-only P13 Multi-Drive Disable 13 1 write-only P14 Multi-Drive Disable 14 1 write-only P15 Multi-Drive Disable 15 1 write-only P16 Multi-Drive Disable 16 1 write-only P17 Multi-Drive Disable 17 1 write-only P18 Multi-Drive Disable 18 1 write-only P19 Multi-Drive Disable 19 1 write-only P2 Multi-Drive Disable 2 1 write-only P20 Multi-Drive Disable 20 1 write-only P21 Multi-Drive Disable 21 1 write-only P22 Multi-Drive Disable 22 1 write-only P23 Multi-Drive Disable 23 1 write-only P24 Multi-Drive Disable 24 1 write-only P25 Multi-Drive Disable 25 1 write-only P26 Multi-Drive Disable 26 1 write-only P27 Multi-Drive Disable 27 1 write-only P28 Multi-Drive Disable 28 1 write-only P29 Multi-Drive Disable 29 1 write-only P3 Multi-Drive Disable 3 1 write-only P30 Multi-Drive Disable 30 1 write-only P31 Multi-Drive Disable 31 1 write-only P4 Multi-Drive Disable 4 1 write-only P5 Multi-Drive Disable 5 1 write-only P6 Multi-Drive Disable 6 1 write-only P7 Multi-Drive Disable 7 1 write-only P8 Multi-Drive Disable 8 1 write-only P9 Multi-Drive Disable 9 1 write-only MDER Multi-driver Enable Register 0x50 32 write-only n 0x0 0x0 P0 Multi-Drive Enable 0 1 write-only P1 Multi-Drive Enable 1 1 write-only P10 Multi-Drive Enable 10 1 write-only P11 Multi-Drive Enable 11 1 write-only P12 Multi-Drive Enable 12 1 write-only P13 Multi-Drive Enable 13 1 write-only P14 Multi-Drive Enable 14 1 write-only P15 Multi-Drive Enable 15 1 write-only P16 Multi-Drive Enable 16 1 write-only P17 Multi-Drive Enable 17 1 write-only P18 Multi-Drive Enable 18 1 write-only P19 Multi-Drive Enable 19 1 write-only P2 Multi-Drive Enable 2 1 write-only P20 Multi-Drive Enable 20 1 write-only P21 Multi-Drive Enable 21 1 write-only P22 Multi-Drive Enable 22 1 write-only P23 Multi-Drive Enable 23 1 write-only P24 Multi-Drive Enable 24 1 write-only P25 Multi-Drive Enable 25 1 write-only P26 Multi-Drive Enable 26 1 write-only P27 Multi-Drive Enable 27 1 write-only P28 Multi-Drive Enable 28 1 write-only P29 Multi-Drive Enable 29 1 write-only P3 Multi-Drive Enable 3 1 write-only P30 Multi-Drive Enable 30 1 write-only P31 Multi-Drive Enable 31 1 write-only P4 Multi-Drive Enable 4 1 write-only P5 Multi-Drive Enable 5 1 write-only P6 Multi-Drive Enable 6 1 write-only P7 Multi-Drive Enable 7 1 write-only P8 Multi-Drive Enable 8 1 write-only P9 Multi-Drive Enable 9 1 write-only MDSR Multi-driver Status Register 0x58 32 read-only n 0x0 0x0 P0 Multi-Drive Status 0 1 read-only P1 Multi-Drive Status 1 1 read-only P10 Multi-Drive Status 10 1 read-only P11 Multi-Drive Status 11 1 read-only P12 Multi-Drive Status 12 1 read-only P13 Multi-Drive Status 13 1 read-only P14 Multi-Drive Status 14 1 read-only P15 Multi-Drive Status 15 1 read-only P16 Multi-Drive Status 16 1 read-only P17 Multi-Drive Status 17 1 read-only P18 Multi-Drive Status 18 1 read-only P19 Multi-Drive Status 19 1 read-only P2 Multi-Drive Status 2 1 read-only P20 Multi-Drive Status 20 1 read-only P21 Multi-Drive Status 21 1 read-only P22 Multi-Drive Status 22 1 read-only P23 Multi-Drive Status 23 1 read-only P24 Multi-Drive Status 24 1 read-only P25 Multi-Drive Status 25 1 read-only P26 Multi-Drive Status 26 1 read-only P27 Multi-Drive Status 27 1 read-only P28 Multi-Drive Status 28 1 read-only P29 Multi-Drive Status 29 1 read-only P3 Multi-Drive Status 3 1 read-only P30 Multi-Drive Status 30 1 read-only P31 Multi-Drive Status 31 1 read-only P4 Multi-Drive Status 4 1 read-only P5 Multi-Drive Status 5 1 read-only P6 Multi-Drive Status 6 1 read-only P7 Multi-Drive Status 7 1 read-only P8 Multi-Drive Status 8 1 read-only P9 Multi-Drive Status 9 1 read-only ODR Output Disable Register 0x14 32 write-only n 0x0 0x0 P0 Output Disable 0 1 write-only P1 Output Disable 1 1 write-only P10 Output Disable 10 1 write-only P11 Output Disable 11 1 write-only P12 Output Disable 12 1 write-only P13 Output Disable 13 1 write-only P14 Output Disable 14 1 write-only P15 Output Disable 15 1 write-only P16 Output Disable 16 1 write-only P17 Output Disable 17 1 write-only P18 Output Disable 18 1 write-only P19 Output Disable 19 1 write-only P2 Output Disable 2 1 write-only P20 Output Disable 20 1 write-only P21 Output Disable 21 1 write-only P22 Output Disable 22 1 write-only P23 Output Disable 23 1 write-only P24 Output Disable 24 1 write-only P25 Output Disable 25 1 write-only P26 Output Disable 26 1 write-only P27 Output Disable 27 1 write-only P28 Output Disable 28 1 write-only P29 Output Disable 29 1 write-only P3 Output Disable 3 1 write-only P30 Output Disable 30 1 write-only P31 Output Disable 31 1 write-only P4 Output Disable 4 1 write-only P5 Output Disable 5 1 write-only P6 Output Disable 6 1 write-only P7 Output Disable 7 1 write-only P8 Output Disable 8 1 write-only P9 Output Disable 9 1 write-only ODSR Output Data Status Register 0x38 32 read-write n 0x0 0x0 P0 Output Data Status 0 1 read-write P1 Output Data Status 1 1 read-write P10 Output Data Status 10 1 read-write P11 Output Data Status 11 1 read-write P12 Output Data Status 12 1 read-write P13 Output Data Status 13 1 read-write P14 Output Data Status 14 1 read-write P15 Output Data Status 15 1 read-write P16 Output Data Status 16 1 read-write P17 Output Data Status 17 1 read-write P18 Output Data Status 18 1 read-write P19 Output Data Status 19 1 read-write P2 Output Data Status 2 1 read-write P20 Output Data Status 20 1 read-write P21 Output Data Status 21 1 read-write P22 Output Data Status 22 1 read-write P23 Output Data Status 23 1 read-write P24 Output Data Status 24 1 read-write P25 Output Data Status 25 1 read-write P26 Output Data Status 26 1 read-write P27 Output Data Status 27 1 read-write P28 Output Data Status 28 1 read-write P29 Output Data Status 29 1 read-write P3 Output Data Status 3 1 read-write P30 Output Data Status 30 1 read-write P31 Output Data Status 31 1 read-write P4 Output Data Status 4 1 read-write P5 Output Data Status 5 1 read-write P6 Output Data Status 6 1 read-write P7 Output Data Status 7 1 read-write P8 Output Data Status 8 1 read-write P9 Output Data Status 9 1 read-write OER Output Enable Register 0x10 32 write-only n 0x0 0x0 P0 Output Enable 0 1 write-only P1 Output Enable 1 1 write-only P10 Output Enable 10 1 write-only P11 Output Enable 11 1 write-only P12 Output Enable 12 1 write-only P13 Output Enable 13 1 write-only P14 Output Enable 14 1 write-only P15 Output Enable 15 1 write-only P16 Output Enable 16 1 write-only P17 Output Enable 17 1 write-only P18 Output Enable 18 1 write-only P19 Output Enable 19 1 write-only P2 Output Enable 2 1 write-only P20 Output Enable 20 1 write-only P21 Output Enable 21 1 write-only P22 Output Enable 22 1 write-only P23 Output Enable 23 1 write-only P24 Output Enable 24 1 write-only P25 Output Enable 25 1 write-only P26 Output Enable 26 1 write-only P27 Output Enable 27 1 write-only P28 Output Enable 28 1 write-only P29 Output Enable 29 1 write-only P3 Output Enable 3 1 write-only P30 Output Enable 30 1 write-only P31 Output Enable 31 1 write-only P4 Output Enable 4 1 write-only P5 Output Enable 5 1 write-only P6 Output Enable 6 1 write-only P7 Output Enable 7 1 write-only P8 Output Enable 8 1 write-only P9 Output Enable 9 1 write-only OSR Output Status Register 0x18 32 read-only n 0x0 0x0 P0 Output Status 0 1 read-only P1 Output Status 1 1 read-only P10 Output Status 10 1 read-only P11 Output Status 11 1 read-only P12 Output Status 12 1 read-only P13 Output Status 13 1 read-only P14 Output Status 14 1 read-only P15 Output Status 15 1 read-only P16 Output Status 16 1 read-only P17 Output Status 17 1 read-only P18 Output Status 18 1 read-only P19 Output Status 19 1 read-only P2 Output Status 2 1 read-only P20 Output Status 20 1 read-only P21 Output Status 21 1 read-only P22 Output Status 22 1 read-only P23 Output Status 23 1 read-only P24 Output Status 24 1 read-only P25 Output Status 25 1 read-only P26 Output Status 26 1 read-only P27 Output Status 27 1 read-only P28 Output Status 28 1 read-only P29 Output Status 29 1 read-only P3 Output Status 3 1 read-only P30 Output Status 30 1 read-only P31 Output Status 31 1 read-only P4 Output Status 4 1 read-only P5 Output Status 5 1 read-only P6 Output Status 6 1 read-only P7 Output Status 7 1 read-only P8 Output Status 8 1 read-only P9 Output Status 9 1 read-only OWDR Output Write Disable 0xA4 32 write-only n 0x0 0x0 P0 Output Write Disable 0 1 write-only P1 Output Write Disable 1 1 write-only P10 Output Write Disable 10 1 write-only P11 Output Write Disable 11 1 write-only P12 Output Write Disable 12 1 write-only P13 Output Write Disable 13 1 write-only P14 Output Write Disable 14 1 write-only P15 Output Write Disable 15 1 write-only P16 Output Write Disable 16 1 write-only P17 Output Write Disable 17 1 write-only P18 Output Write Disable 18 1 write-only P19 Output Write Disable 19 1 write-only P2 Output Write Disable 2 1 write-only P20 Output Write Disable 20 1 write-only P21 Output Write Disable 21 1 write-only P22 Output Write Disable 22 1 write-only P23 Output Write Disable 23 1 write-only P24 Output Write Disable 24 1 write-only P25 Output Write Disable 25 1 write-only P26 Output Write Disable 26 1 write-only P27 Output Write Disable 27 1 write-only P28 Output Write Disable 28 1 write-only P29 Output Write Disable 29 1 write-only P3 Output Write Disable 3 1 write-only P30 Output Write Disable 30 1 write-only P31 Output Write Disable 31 1 write-only P4 Output Write Disable 4 1 write-only P5 Output Write Disable 5 1 write-only P6 Output Write Disable 6 1 write-only P7 Output Write Disable 7 1 write-only P8 Output Write Disable 8 1 write-only P9 Output Write Disable 9 1 write-only OWER Output Write Enable 0xA0 32 write-only n 0x0 0x0 P0 Output Write Enable 0 1 write-only P1 Output Write Enable 1 1 write-only P10 Output Write Enable 10 1 write-only P11 Output Write Enable 11 1 write-only P12 Output Write Enable 12 1 write-only P13 Output Write Enable 13 1 write-only P14 Output Write Enable 14 1 write-only P15 Output Write Enable 15 1 write-only P16 Output Write Enable 16 1 write-only P17 Output Write Enable 17 1 write-only P18 Output Write Enable 18 1 write-only P19 Output Write Enable 19 1 write-only P2 Output Write Enable 2 1 write-only P20 Output Write Enable 20 1 write-only P21 Output Write Enable 21 1 write-only P22 Output Write Enable 22 1 write-only P23 Output Write Enable 23 1 write-only P24 Output Write Enable 24 1 write-only P25 Output Write Enable 25 1 write-only P26 Output Write Enable 26 1 write-only P27 Output Write Enable 27 1 write-only P28 Output Write Enable 28 1 write-only P29 Output Write Enable 29 1 write-only P3 Output Write Enable 3 1 write-only P30 Output Write Enable 30 1 write-only P31 Output Write Enable 31 1 write-only P4 Output Write Enable 4 1 write-only P5 Output Write Enable 5 1 write-only P6 Output Write Enable 6 1 write-only P7 Output Write Enable 7 1 write-only P8 Output Write Enable 8 1 write-only P9 Output Write Enable 9 1 write-only OWSR Output Write Status Register 0xA8 32 read-only n 0x0 0x0 P0 Output Write Status 0 1 read-only P1 Output Write Status 1 1 read-only P10 Output Write Status 10 1 read-only P11 Output Write Status 11 1 read-only P12 Output Write Status 12 1 read-only P13 Output Write Status 13 1 read-only P14 Output Write Status 14 1 read-only P15 Output Write Status 15 1 read-only P16 Output Write Status 16 1 read-only P17 Output Write Status 17 1 read-only P18 Output Write Status 18 1 read-only P19 Output Write Status 19 1 read-only P2 Output Write Status 2 1 read-only P20 Output Write Status 20 1 read-only P21 Output Write Status 21 1 read-only P22 Output Write Status 22 1 read-only P23 Output Write Status 23 1 read-only P24 Output Write Status 24 1 read-only P25 Output Write Status 25 1 read-only P26 Output Write Status 26 1 read-only P27 Output Write Status 27 1 read-only P28 Output Write Status 28 1 read-only P29 Output Write Status 29 1 read-only P3 Output Write Status 3 1 read-only P30 Output Write Status 30 1 read-only P31 Output Write Status 31 1 read-only P4 Output Write Status 4 1 read-only P5 Output Write Status 5 1 read-only P6 Output Write Status 6 1 read-only P7 Output Write Status 7 1 read-only P8 Output Write Status 8 1 read-only P9 Output Write Status 9 1 read-only PDR PIO Disable Register 0x4 32 write-only n 0x0 0x0 P0 PIO Disable 0 1 write-only P1 PIO Disable 1 1 write-only P10 PIO Disable 10 1 write-only P11 PIO Disable 11 1 write-only P12 PIO Disable 12 1 write-only P13 PIO Disable 13 1 write-only P14 PIO Disable 14 1 write-only P15 PIO Disable 15 1 write-only P16 PIO Disable 16 1 write-only P17 PIO Disable 17 1 write-only P18 PIO Disable 18 1 write-only P19 PIO Disable 19 1 write-only P2 PIO Disable 2 1 write-only P20 PIO Disable 20 1 write-only P21 PIO Disable 21 1 write-only P22 PIO Disable 22 1 write-only P23 PIO Disable 23 1 write-only P24 PIO Disable 24 1 write-only P25 PIO Disable 25 1 write-only P26 PIO Disable 26 1 write-only P27 PIO Disable 27 1 write-only P28 PIO Disable 28 1 write-only P29 PIO Disable 29 1 write-only P3 PIO Disable 3 1 write-only P30 PIO Disable 30 1 write-only P31 PIO Disable 31 1 write-only P4 PIO Disable 4 1 write-only P5 PIO Disable 5 1 write-only P6 PIO Disable 6 1 write-only P7 PIO Disable 7 1 write-only P8 PIO Disable 8 1 write-only P9 PIO Disable 9 1 write-only PDSR Pin Data Status Register 0x3C 32 read-only n 0x0 0x0 P0 Output Data Status 0 1 read-only P1 Output Data Status 1 1 read-only P10 Output Data Status 10 1 read-only P11 Output Data Status 11 1 read-only P12 Output Data Status 12 1 read-only P13 Output Data Status 13 1 read-only P14 Output Data Status 14 1 read-only P15 Output Data Status 15 1 read-only P16 Output Data Status 16 1 read-only P17 Output Data Status 17 1 read-only P18 Output Data Status 18 1 read-only P19 Output Data Status 19 1 read-only P2 Output Data Status 2 1 read-only P20 Output Data Status 20 1 read-only P21 Output Data Status 21 1 read-only P22 Output Data Status 22 1 read-only P23 Output Data Status 23 1 read-only P24 Output Data Status 24 1 read-only P25 Output Data Status 25 1 read-only P26 Output Data Status 26 1 read-only P27 Output Data Status 27 1 read-only P28 Output Data Status 28 1 read-only P29 Output Data Status 29 1 read-only P3 Output Data Status 3 1 read-only P30 Output Data Status 30 1 read-only P31 Output Data Status 31 1 read-only P4 Output Data Status 4 1 read-only P5 Output Data Status 5 1 read-only P6 Output Data Status 6 1 read-only P7 Output Data Status 7 1 read-only P8 Output Data Status 8 1 read-only P9 Output Data Status 9 1 read-only PER PIO Enable Register 0x0 32 write-only n 0x0 0x0 P0 PIO Enable 0 1 write-only P1 PIO Enable 1 1 write-only P10 PIO Enable 10 1 write-only P11 PIO Enable 11 1 write-only P12 PIO Enable 12 1 write-only P13 PIO Enable 13 1 write-only P14 PIO Enable 14 1 write-only P15 PIO Enable 15 1 write-only P16 PIO Enable 16 1 write-only P17 PIO Enable 17 1 write-only P18 PIO Enable 18 1 write-only P19 PIO Enable 19 1 write-only P2 PIO Enable 2 1 write-only P20 PIO Enable 20 1 write-only P21 PIO Enable 21 1 write-only P22 PIO Enable 22 1 write-only P23 PIO Enable 23 1 write-only P24 PIO Enable 24 1 write-only P25 PIO Enable 25 1 write-only P26 PIO Enable 26 1 write-only P27 PIO Enable 27 1 write-only P28 PIO Enable 28 1 write-only P29 PIO Enable 29 1 write-only P3 PIO Enable 3 1 write-only P30 PIO Enable 30 1 write-only P31 PIO Enable 31 1 write-only P4 PIO Enable 4 1 write-only P5 PIO Enable 5 1 write-only P6 PIO Enable 6 1 write-only P7 PIO Enable 7 1 write-only P8 PIO Enable 8 1 write-only P9 PIO Enable 9 1 write-only PPDDR Pad Pull-down Disable Register 0x90 32 write-only n 0x0 0x0 P0 Pull-Down Disable 0 1 write-only P1 Pull-Down Disable 1 1 write-only P10 Pull-Down Disable 10 1 write-only P11 Pull-Down Disable 11 1 write-only P12 Pull-Down Disable 12 1 write-only P13 Pull-Down Disable 13 1 write-only P14 Pull-Down Disable 14 1 write-only P15 Pull-Down Disable 15 1 write-only P16 Pull-Down Disable 16 1 write-only P17 Pull-Down Disable 17 1 write-only P18 Pull-Down Disable 18 1 write-only P19 Pull-Down Disable 19 1 write-only P2 Pull-Down Disable 2 1 write-only P20 Pull-Down Disable 20 1 write-only P21 Pull-Down Disable 21 1 write-only P22 Pull-Down Disable 22 1 write-only P23 Pull-Down Disable 23 1 write-only P24 Pull-Down Disable 24 1 write-only P25 Pull-Down Disable 25 1 write-only P26 Pull-Down Disable 26 1 write-only P27 Pull-Down Disable 27 1 write-only P28 Pull-Down Disable 28 1 write-only P29 Pull-Down Disable 29 1 write-only P3 Pull-Down Disable 3 1 write-only P30 Pull-Down Disable 30 1 write-only P31 Pull-Down Disable 31 1 write-only P4 Pull-Down Disable 4 1 write-only P5 Pull-Down Disable 5 1 write-only P6 Pull-Down Disable 6 1 write-only P7 Pull-Down Disable 7 1 write-only P8 Pull-Down Disable 8 1 write-only P9 Pull-Down Disable 9 1 write-only PPDER Pad Pull-down Enable Register 0x94 32 write-only n 0x0 0x0 P0 Pull-Down Enable 0 1 write-only P1 Pull-Down Enable 1 1 write-only P10 Pull-Down Enable 10 1 write-only P11 Pull-Down Enable 11 1 write-only P12 Pull-Down Enable 12 1 write-only P13 Pull-Down Enable 13 1 write-only P14 Pull-Down Enable 14 1 write-only P15 Pull-Down Enable 15 1 write-only P16 Pull-Down Enable 16 1 write-only P17 Pull-Down Enable 17 1 write-only P18 Pull-Down Enable 18 1 write-only P19 Pull-Down Enable 19 1 write-only P2 Pull-Down Enable 2 1 write-only P20 Pull-Down Enable 20 1 write-only P21 Pull-Down Enable 21 1 write-only P22 Pull-Down Enable 22 1 write-only P23 Pull-Down Enable 23 1 write-only P24 Pull-Down Enable 24 1 write-only P25 Pull-Down Enable 25 1 write-only P26 Pull-Down Enable 26 1 write-only P27 Pull-Down Enable 27 1 write-only P28 Pull-Down Enable 28 1 write-only P29 Pull-Down Enable 29 1 write-only P3 Pull-Down Enable 3 1 write-only P30 Pull-Down Enable 30 1 write-only P31 Pull-Down Enable 31 1 write-only P4 Pull-Down Enable 4 1 write-only P5 Pull-Down Enable 5 1 write-only P6 Pull-Down Enable 6 1 write-only P7 Pull-Down Enable 7 1 write-only P8 Pull-Down Enable 8 1 write-only P9 Pull-Down Enable 9 1 write-only PPDSR Pad Pull-down Status Register 0x98 32 read-only n 0x0 0x0 P0 Pull-Down Status 0 1 read-only P1 Pull-Down Status 1 1 read-only P10 Pull-Down Status 10 1 read-only P11 Pull-Down Status 11 1 read-only P12 Pull-Down Status 12 1 read-only P13 Pull-Down Status 13 1 read-only P14 Pull-Down Status 14 1 read-only P15 Pull-Down Status 15 1 read-only P16 Pull-Down Status 16 1 read-only P17 Pull-Down Status 17 1 read-only P18 Pull-Down Status 18 1 read-only P19 Pull-Down Status 19 1 read-only P2 Pull-Down Status 2 1 read-only P20 Pull-Down Status 20 1 read-only P21 Pull-Down Status 21 1 read-only P22 Pull-Down Status 22 1 read-only P23 Pull-Down Status 23 1 read-only P24 Pull-Down Status 24 1 read-only P25 Pull-Down Status 25 1 read-only P26 Pull-Down Status 26 1 read-only P27 Pull-Down Status 27 1 read-only P28 Pull-Down Status 28 1 read-only P29 Pull-Down Status 29 1 read-only P3 Pull-Down Status 3 1 read-only P30 Pull-Down Status 30 1 read-only P31 Pull-Down Status 31 1 read-only P4 Pull-Down Status 4 1 read-only P5 Pull-Down Status 5 1 read-only P6 Pull-Down Status 6 1 read-only P7 Pull-Down Status 7 1 read-only P8 Pull-Down Status 8 1 read-only P9 Pull-Down Status 9 1 read-only PSR PIO Status Register 0x8 32 read-only n 0x0 0x0 P0 PIO Status 0 1 read-only P1 PIO Status 1 1 read-only P10 PIO Status 10 1 read-only P11 PIO Status 11 1 read-only P12 PIO Status 12 1 read-only P13 PIO Status 13 1 read-only P14 PIO Status 14 1 read-only P15 PIO Status 15 1 read-only P16 PIO Status 16 1 read-only P17 PIO Status 17 1 read-only P18 PIO Status 18 1 read-only P19 PIO Status 19 1 read-only P2 PIO Status 2 1 read-only P20 PIO Status 20 1 read-only P21 PIO Status 21 1 read-only P22 PIO Status 22 1 read-only P23 PIO Status 23 1 read-only P24 PIO Status 24 1 read-only P25 PIO Status 25 1 read-only P26 PIO Status 26 1 read-only P27 PIO Status 27 1 read-only P28 PIO Status 28 1 read-only P29 PIO Status 29 1 read-only P3 PIO Status 3 1 read-only P30 PIO Status 30 1 read-only P31 PIO Status 31 1 read-only P4 PIO Status 4 1 read-only P5 PIO Status 5 1 read-only P6 PIO Status 6 1 read-only P7 PIO Status 7 1 read-only P8 PIO Status 8 1 read-only P9 PIO Status 9 1 read-only PUDR Pull-up Disable Register 0x60 32 write-only n 0x0 0x0 P0 Pull-Up Disable 0 1 write-only P1 Pull-Up Disable 1 1 write-only P10 Pull-Up Disable 10 1 write-only P11 Pull-Up Disable 11 1 write-only P12 Pull-Up Disable 12 1 write-only P13 Pull-Up Disable 13 1 write-only P14 Pull-Up Disable 14 1 write-only P15 Pull-Up Disable 15 1 write-only P16 Pull-Up Disable 16 1 write-only P17 Pull-Up Disable 17 1 write-only P18 Pull-Up Disable 18 1 write-only P19 Pull-Up Disable 19 1 write-only P2 Pull-Up Disable 2 1 write-only P20 Pull-Up Disable 20 1 write-only P21 Pull-Up Disable 21 1 write-only P22 Pull-Up Disable 22 1 write-only P23 Pull-Up Disable 23 1 write-only P24 Pull-Up Disable 24 1 write-only P25 Pull-Up Disable 25 1 write-only P26 Pull-Up Disable 26 1 write-only P27 Pull-Up Disable 27 1 write-only P28 Pull-Up Disable 28 1 write-only P29 Pull-Up Disable 29 1 write-only P3 Pull-Up Disable 3 1 write-only P30 Pull-Up Disable 30 1 write-only P31 Pull-Up Disable 31 1 write-only P4 Pull-Up Disable 4 1 write-only P5 Pull-Up Disable 5 1 write-only P6 Pull-Up Disable 6 1 write-only P7 Pull-Up Disable 7 1 write-only P8 Pull-Up Disable 8 1 write-only P9 Pull-Up Disable 9 1 write-only PUER Pull-up Enable Register 0x64 32 write-only n 0x0 0x0 P0 Pull-Up Enable 0 1 write-only P1 Pull-Up Enable 1 1 write-only P10 Pull-Up Enable 10 1 write-only P11 Pull-Up Enable 11 1 write-only P12 Pull-Up Enable 12 1 write-only P13 Pull-Up Enable 13 1 write-only P14 Pull-Up Enable 14 1 write-only P15 Pull-Up Enable 15 1 write-only P16 Pull-Up Enable 16 1 write-only P17 Pull-Up Enable 17 1 write-only P18 Pull-Up Enable 18 1 write-only P19 Pull-Up Enable 19 1 write-only P2 Pull-Up Enable 2 1 write-only P20 Pull-Up Enable 20 1 write-only P21 Pull-Up Enable 21 1 write-only P22 Pull-Up Enable 22 1 write-only P23 Pull-Up Enable 23 1 write-only P24 Pull-Up Enable 24 1 write-only P25 Pull-Up Enable 25 1 write-only P26 Pull-Up Enable 26 1 write-only P27 Pull-Up Enable 27 1 write-only P28 Pull-Up Enable 28 1 write-only P29 Pull-Up Enable 29 1 write-only P3 Pull-Up Enable 3 1 write-only P30 Pull-Up Enable 30 1 write-only P31 Pull-Up Enable 31 1 write-only P4 Pull-Up Enable 4 1 write-only P5 Pull-Up Enable 5 1 write-only P6 Pull-Up Enable 6 1 write-only P7 Pull-Up Enable 7 1 write-only P8 Pull-Up Enable 8 1 write-only P9 Pull-Up Enable 9 1 write-only PUSR Pad Pull-up Status Register 0x68 32 read-only n 0x0 0x0 P0 Pull-Up Status 0 1 read-only P1 Pull-Up Status 1 1 read-only P10 Pull-Up Status 10 1 read-only P11 Pull-Up Status 11 1 read-only P12 Pull-Up Status 12 1 read-only P13 Pull-Up Status 13 1 read-only P14 Pull-Up Status 14 1 read-only P15 Pull-Up Status 15 1 read-only P16 Pull-Up Status 16 1 read-only P17 Pull-Up Status 17 1 read-only P18 Pull-Up Status 18 1 read-only P19 Pull-Up Status 19 1 read-only P2 Pull-Up Status 2 1 read-only P20 Pull-Up Status 20 1 read-only P21 Pull-Up Status 21 1 read-only P22 Pull-Up Status 22 1 read-only P23 Pull-Up Status 23 1 read-only P24 Pull-Up Status 24 1 read-only P25 Pull-Up Status 25 1 read-only P26 Pull-Up Status 26 1 read-only P27 Pull-Up Status 27 1 read-only P28 Pull-Up Status 28 1 read-only P29 Pull-Up Status 29 1 read-only P3 Pull-Up Status 3 1 read-only P30 Pull-Up Status 30 1 read-only P31 Pull-Up Status 31 1 read-only P4 Pull-Up Status 4 1 read-only P5 Pull-Up Status 5 1 read-only P6 Pull-Up Status 6 1 read-only P7 Pull-Up Status 7 1 read-only P8 Pull-Up Status 8 1 read-only P9 Pull-Up Status 9 1 read-only REHLSR Rising Edge/ High-Level Select Register 0xD4 32 write-only n 0x0 0x0 P0 Rising Edge /High-Level Interrupt Selection 0 1 write-only P1 Rising Edge /High-Level Interrupt Selection 1 1 write-only P10 Rising Edge /High-Level Interrupt Selection 10 1 write-only P11 Rising Edge /High-Level Interrupt Selection 11 1 write-only P12 Rising Edge /High-Level Interrupt Selection 12 1 write-only P13 Rising Edge /High-Level Interrupt Selection 13 1 write-only P14 Rising Edge /High-Level Interrupt Selection 14 1 write-only P15 Rising Edge /High-Level Interrupt Selection 15 1 write-only P16 Rising Edge /High-Level Interrupt Selection 16 1 write-only P17 Rising Edge /High-Level Interrupt Selection 17 1 write-only P18 Rising Edge /High-Level Interrupt Selection 18 1 write-only P19 Rising Edge /High-Level Interrupt Selection 19 1 write-only P2 Rising Edge /High-Level Interrupt Selection 2 1 write-only P20 Rising Edge /High-Level Interrupt Selection 20 1 write-only P21 Rising Edge /High-Level Interrupt Selection 21 1 write-only P22 Rising Edge /High-Level Interrupt Selection 22 1 write-only P23 Rising Edge /High-Level Interrupt Selection 23 1 write-only P24 Rising Edge /High-Level Interrupt Selection 24 1 write-only P25 Rising Edge /High-Level Interrupt Selection 25 1 write-only P26 Rising Edge /High-Level Interrupt Selection 26 1 write-only P27 Rising Edge /High-Level Interrupt Selection 27 1 write-only P28 Rising Edge /High-Level Interrupt Selection 28 1 write-only P29 Rising Edge /High-Level Interrupt Selection 29 1 write-only P3 Rising Edge /High-Level Interrupt Selection 3 1 write-only P30 Rising Edge /High-Level Interrupt Selection 30 1 write-only P31 Rising Edge /High-Level Interrupt Selection 31 1 write-only P4 Rising Edge /High-Level Interrupt Selection 4 1 write-only P5 Rising Edge /High-Level Interrupt Selection 5 1 write-only P6 Rising Edge /High-Level Interrupt Selection 6 1 write-only P7 Rising Edge /High-Level Interrupt Selection 7 1 write-only P8 Rising Edge /High-Level Interrupt Selection 8 1 write-only P9 Rising Edge /High-Level Interrupt Selection 9 1 write-only SCDR Slow Clock Divider Debouncing Register 0x8C 32 read-write n 0x0 0x0 DIV Slow Clock Divider Selection for Debouncing 0 14 read-write SCHMITT Schmitt Trigger Register 0x100 32 read-write n 0x0 0x0 SCHMITT0 Schmitt Trigger Control 0 1 read-write SCHMITT1 Schmitt Trigger Control 1 1 read-write SCHMITT10 Schmitt Trigger Control 10 1 read-write SCHMITT11 Schmitt Trigger Control 11 1 read-write SCHMITT12 Schmitt Trigger Control 12 1 read-write SCHMITT13 Schmitt Trigger Control 13 1 read-write SCHMITT14 Schmitt Trigger Control 14 1 read-write SCHMITT15 Schmitt Trigger Control 15 1 read-write SCHMITT16 Schmitt Trigger Control 16 1 read-write SCHMITT17 Schmitt Trigger Control 17 1 read-write SCHMITT18 Schmitt Trigger Control 18 1 read-write SCHMITT19 Schmitt Trigger Control 19 1 read-write SCHMITT2 Schmitt Trigger Control 2 1 read-write SCHMITT20 Schmitt Trigger Control 20 1 read-write SCHMITT21 Schmitt Trigger Control 21 1 read-write SCHMITT22 Schmitt Trigger Control 22 1 read-write SCHMITT23 Schmitt Trigger Control 23 1 read-write SCHMITT24 Schmitt Trigger Control 24 1 read-write SCHMITT25 Schmitt Trigger Control 25 1 read-write SCHMITT26 Schmitt Trigger Control 26 1 read-write SCHMITT27 Schmitt Trigger Control 27 1 read-write SCHMITT28 Schmitt Trigger Control 28 1 read-write SCHMITT29 Schmitt Trigger Control 29 1 read-write SCHMITT3 Schmitt Trigger Control 3 1 read-write SCHMITT30 Schmitt Trigger Control 30 1 read-write SCHMITT31 Schmitt Trigger Control 31 1 read-write SCHMITT4 Schmitt Trigger Control 4 1 read-write SCHMITT5 Schmitt Trigger Control 5 1 read-write SCHMITT6 Schmitt Trigger Control 6 1 read-write SCHMITT7 Schmitt Trigger Control 7 1 read-write SCHMITT8 Schmitt Trigger Control 8 1 read-write SCHMITT9 Schmitt Trigger Control 9 1 read-write SODR Set Output Data Register 0x30 32 write-only n 0x0 0x0 P0 Set Output Data 0 1 write-only P1 Set Output Data 1 1 write-only P10 Set Output Data 10 1 write-only P11 Set Output Data 11 1 write-only P12 Set Output Data 12 1 write-only P13 Set Output Data 13 1 write-only P14 Set Output Data 14 1 write-only P15 Set Output Data 15 1 write-only P16 Set Output Data 16 1 write-only P17 Set Output Data 17 1 write-only P18 Set Output Data 18 1 write-only P19 Set Output Data 19 1 write-only P2 Set Output Data 2 1 write-only P20 Set Output Data 20 1 write-only P21 Set Output Data 21 1 write-only P22 Set Output Data 22 1 write-only P23 Set Output Data 23 1 write-only P24 Set Output Data 24 1 write-only P25 Set Output Data 25 1 write-only P26 Set Output Data 26 1 write-only P27 Set Output Data 27 1 write-only P28 Set Output Data 28 1 write-only P29 Set Output Data 29 1 write-only P3 Set Output Data 3 1 write-only P30 Set Output Data 30 1 write-only P31 Set Output Data 31 1 write-only P4 Set Output Data 4 1 write-only P5 Set Output Data 5 1 write-only P6 Set Output Data 6 1 write-only P7 Set Output Data 7 1 write-only P8 Set Output Data 8 1 write-only P9 Set Output Data 9 1 write-only WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key. 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 0x50494F WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only PMC Power Management Controller PMC 0x0 0x0 0x140 registers n PMC 5 CKGR_MCFR Main Clock Frequency Register 0x24 32 read-write n 0x0 0x0 MAINF Main Clock Frequency 0 16 read-write MAINFRDY Main Clock Ready 16 1 read-write RCMEAS RC Oscillator Frequency Measure (write-only) 20 1 read-write CKGR_MOR Main Oscillator Register 0x20 32 read-write n 0x0 0x0 CFDEN Clock Failure Detector Enable 25 1 read-write KEY Write Access Password 16 8 read-write PASSWD Writing any other value in this field aborts the write operation.Always reads as 0. 0x37 MOSCRCEN Main On-Chip RC Oscillator Enable 3 1 read-write MOSCRCF Main On-Chip RC Oscillator Frequency Selection 4 3 read-write 8_MHz The Fast RC Oscillator Frequency is at 8 MHz (default) 0x0 16_MHz The Fast RC Oscillator Frequency is at 16 MHz 0x1 24_MHz The Fast RC Oscillator Frequency is at 24 MHz 0x2 MOSCSEL Main Oscillator Selection 24 1 read-write MOSCXTBY Main Crystal Oscillator Bypass 1 1 read-write MOSCXTEN Main Crystal Oscillator Enable 0 1 read-write MOSCXTST Main Crystal Oscillator Start-up Time 8 8 read-write WAITMODE Wait Mode Command 2 1 read-write CKGR_PLLAR PLLA Register 0x28 32 read-write n 0x0 0x0 MULA PLLA Multiplier 16 12 read-write PLLACOUNT PLLA Counter 8 6 read-write PLLAEN PLLA Control 0 8 read-write FOCR Fault Output Clear Register 0x78 32 write-only n 0x0 0x0 FOCLR Fault Output Clear 0 1 write-only FSMR Fast Startup Mode Register 0x70 32 read-write n 0x0 0x0 FLPM Flash Low-power Mode 21 2 read-write FLASH_STANDBY Flash is in Standby Mode when system enters Wait Mode 0x0 FLASH_DEEP_POWERDOWN Flash is in deep-power-down mode when system enters Wait Mode 0x1 FLASH_IDLE idle mode 0x2 FSTT0 Fast Startup Input Enable 0 0 1 read-write FSTT1 Fast Startup Input Enable 1 1 1 read-write FSTT10 Fast Startup Input Enable 10 10 1 read-write FSTT11 Fast Startup Input Enable 11 11 1 read-write FSTT12 Fast Startup Input Enable 12 12 1 read-write FSTT13 Fast Startup Input Enable 13 13 1 read-write FSTT14 Fast Startup Input Enable 14 14 1 read-write FSTT15 Fast Startup Input Enable 15 15 1 read-write FSTT2 Fast Startup Input Enable 2 2 1 read-write FSTT3 Fast Startup Input Enable 3 3 1 read-write FSTT4 Fast Startup Input Enable 4 4 1 read-write FSTT5 Fast Startup Input Enable 5 5 1 read-write FSTT6 Fast Startup Input Enable 6 6 1 read-write FSTT7 Fast Startup Input Enable 7 7 1 read-write FSTT8 Fast Startup Input Enable 8 8 1 read-write FSTT9 Fast Startup Input Enable 9 9 1 read-write LPM Low-power Mode 20 1 read-write RTCAL RTC Alarm Enable 17 1 read-write RTTAL RTT Alarm Enable 16 1 read-write FSPR Fast Startup Polarity Register 0x74 32 read-write n 0x0 0x0 FSTP0 Fast Startup Input Polarityx 0 1 read-write FSTP1 Fast Startup Input Polarityx 1 1 read-write FSTP10 Fast Startup Input Polarityx 10 1 read-write FSTP11 Fast Startup Input Polarityx 11 1 read-write FSTP12 Fast Startup Input Polarityx 12 1 read-write FSTP13 Fast Startup Input Polarityx 13 1 read-write FSTP14 Fast Startup Input Polarityx 14 1 read-write FSTP15 Fast Startup Input Polarityx 15 1 read-write FSTP2 Fast Startup Input Polarityx 2 1 read-write FSTP3 Fast Startup Input Polarityx 3 1 read-write FSTP4 Fast Startup Input Polarityx 4 1 read-write FSTP5 Fast Startup Input Polarityx 5 1 read-write FSTP6 Fast Startup Input Polarityx 6 1 read-write FSTP7 Fast Startup Input Polarityx 7 1 read-write FSTP8 Fast Startup Input Polarityx 8 1 read-write FSTP9 Fast Startup Input Polarityx 9 1 read-write IDR Interrupt Disable Register 0x64 32 write-only n 0x0 0x0 CFDEV Clock Failure Detector Event Interrupt Disable 18 1 write-only LOCKA PLLA Lock Interrupt Disable 1 1 write-only MCKRDY Master Clock Ready Interrupt Disable 3 1 write-only MOSCRCS Main On-Chip RC Status Interrupt Disable 17 1 write-only MOSCSELS Main Oscillator Selection Status Interrupt Disable 16 1 write-only MOSCXTS Main Crystal Oscillator Status Interrupt Disable 0 1 write-only PCKRDY0 Programmable Clock Ready 0 Interrupt Disable 8 1 write-only PCKRDY1 Programmable Clock Ready 1 Interrupt Disable 9 1 write-only PCKRDY2 Programmable Clock Ready 2 Interrupt Disable 10 1 write-only IER Interrupt Enable Register 0x60 32 write-only n 0x0 0x0 CFDEV Clock Failure Detector Event Interrupt Enable 18 1 write-only LOCKA PLLA Lock Interrupt Enable 1 1 write-only MCKRDY Master Clock Ready Interrupt Enable 3 1 write-only MOSCRCS Main On-Chip RC Status Interrupt Enable 17 1 write-only MOSCSELS Main Oscillator Selection Status Interrupt Enable 16 1 write-only MOSCXTS Main Crystal Oscillator Status Interrupt Enable 0 1 write-only PCKRDY0 Programmable Clock Ready 0 Interrupt Enable 8 1 write-only PCKRDY1 Programmable Clock Ready 1 Interrupt Enable 9 1 write-only PCKRDY2 Programmable Clock Ready 2 Interrupt Enable 10 1 write-only IMR Interrupt Mask Register 0x6C 32 read-only n 0x0 0x0 CFDEV Clock Failure Detector Event Interrupt Mask 18 1 read-only LOCKA PLLA Lock Interrupt Mask 1 1 read-only MCKRDY Master Clock Ready Interrupt Mask 3 1 read-only MOSCRCS Main On-Chip RC Status Interrupt Mask 17 1 read-only MOSCSELS Main Oscillator Selection Status Interrupt Mask 16 1 read-only MOSCXTS Main Crystal Oscillator Status Interrupt Mask 0 1 read-only PCKRDY0 Programmable Clock Ready 0 Interrupt Mask 8 1 read-only PCKRDY1 Programmable Clock Ready 1 Interrupt Mask 9 1 read-only PCKRDY2 Programmable Clock Ready 2 Interrupt Mask 10 1 read-only MCKR Master Clock Register 0x30 32 read-write n 0x0 0x0 CSS Master Clock Source Selection 0 2 read-write SLOW_CLK Slow Clock is selected 0x0 MAIN_CLK Main Clock is selected 0x1 PLLA_CLK PLLA Clock is selected 0x2 PLLADIV2 PLLA Divisor by 2 12 1 read-write PRES Processor Clock Prescaler 4 3 read-write CLK_1 Selected clock 0x0 CLK_2 Selected clock divided by 2 0x1 CLK_4 Selected clock divided by 4 0x2 CLK_8 Selected clock divided by 8 0x3 CLK_16 Selected clock divided by 16 0x4 CLK_32 Selected clock divided by 32 0x5 CLK_64 Selected clock divided by 64 0x6 CLK_3 Selected clock divided by 3 0x7 OCR Oscillator Calibration Register 0x110 32 read-write n 0x0 0x0 CAL16 RC Oscillator Calibration bits for 16 MHz 8 7 read-write CAL24 RC Oscillator Calibration bits for 24 MHz 16 7 read-write CAL8 RC Oscillator Calibration bits for 8 MHz 0 7 read-write SEL16 Selection of RC Oscillator Calibration bits for 16 MHz 15 1 read-write SEL24 Selection of RC Oscillator Calibration bits for 24 MHz 23 1 read-write SEL8 Selection of RC Oscillator Calibration bits for 8 MHz 7 1 read-write PCDR0 Peripheral Clock Disable Register 0 0x14 32 write-only n 0x0 0x0 PID10 Peripheral Clock 10 Disable 10 1 write-only PID11 Peripheral Clock 11 Disable 11 1 write-only PID12 Peripheral Clock 12 Disable 12 1 write-only PID13 Peripheral Clock 13 Disable 13 1 write-only PID14 Peripheral Clock 14 Disable 14 1 write-only PID15 Peripheral Clock 15 Disable 15 1 write-only PID16 Peripheral Clock 16 Disable 16 1 write-only PID17 Peripheral Clock 17 Disable 17 1 write-only PID18 Peripheral Clock 18 Disable 18 1 write-only PID19 Peripheral Clock 19 Disable 19 1 write-only PID20 Peripheral Clock 20 Disable 20 1 write-only PID21 Peripheral Clock 21 Disable 21 1 write-only PID22 Peripheral Clock 22 Disable 22 1 write-only PID23 Peripheral Clock 23 Disable 23 1 write-only PID24 Peripheral Clock 24 Disable 24 1 write-only PID25 Peripheral Clock 25 Disable 25 1 write-only PID26 Peripheral Clock 26 Disable 26 1 write-only PID27 Peripheral Clock 27 Disable 27 1 write-only PID28 Peripheral Clock 28 Disable 28 1 write-only PID29 Peripheral Clock 29 Disable 29 1 write-only PID8 Peripheral Clock 8 Disable 8 1 write-only PID9 Peripheral Clock 9 Disable 9 1 write-only PCER0 Peripheral Clock Enable Register 0 0x10 32 write-only n 0x0 0x0 PID10 Peripheral Clock 10 Enable 10 1 write-only PID11 Peripheral Clock 11 Enable 11 1 write-only PID12 Peripheral Clock 12 Enable 12 1 write-only PID13 Peripheral Clock 13 Enable 13 1 write-only PID14 Peripheral Clock 14 Enable 14 1 write-only PID15 Peripheral Clock 15 Enable 15 1 write-only PID16 Peripheral Clock 16 Enable 16 1 write-only PID17 Peripheral Clock 17 Enable 17 1 write-only PID18 Peripheral Clock 18 Enable 18 1 write-only PID19 Peripheral Clock 19 Enable 19 1 write-only PID20 Peripheral Clock 20 Enable 20 1 write-only PID21 Peripheral Clock 21 Enable 21 1 write-only PID22 Peripheral Clock 22 Enable 22 1 write-only PID23 Peripheral Clock 23 Enable 23 1 write-only PID24 Peripheral Clock 24 Enable 24 1 write-only PID25 Peripheral Clock 25 Enable 25 1 write-only PID26 Peripheral Clock 26 Enable 26 1 write-only PID27 Peripheral Clock 27 Enable 27 1 write-only PID28 Peripheral Clock 28 Enable 28 1 write-only PID29 Peripheral Clock 29 Enable 29 1 write-only PID8 Peripheral Clock 8 Enable 8 1 write-only PID9 Peripheral Clock 9 Enable 9 1 write-only PCK0 Programmable Clock 0 Register 0x40 32 read-write n CSS Master Clock Source Selection 0 3 read-write SLOW_CLK Slow Clock is selected 0x0 MAIN_CLK Main Clock is selected 0x1 PLLA_CLK PLLA Clock is selected 0x2 MCK Master Clock is selected 0x4 PRES Programmable Clock Prescaler 4 3 read-write CLK_1 Selected clock 0x0 CLK_2 Selected clock divided by 2 0x1 CLK_4 Selected clock divided by 4 0x2 CLK_8 Selected clock divided by 8 0x3 CLK_16 Selected clock divided by 16 0x4 CLK_32 Selected clock divided by 32 0x5 CLK_64 Selected clock divided by 64 0x6 PCK1 Programmable Clock 0 Register 0x44 32 read-write n CSS Master Clock Source Selection 0 3 read-write SLOW_CLK Slow Clock is selected 0x0 MAIN_CLK Main Clock is selected 0x1 PLLA_CLK PLLA Clock is selected 0x2 MCK Master Clock is selected 0x4 PRES Programmable Clock Prescaler 4 3 read-write CLK_1 Selected clock 0x0 CLK_2 Selected clock divided by 2 0x1 CLK_4 Selected clock divided by 4 0x2 CLK_8 Selected clock divided by 8 0x3 CLK_16 Selected clock divided by 16 0x4 CLK_32 Selected clock divided by 32 0x5 CLK_64 Selected clock divided by 64 0x6 PCK2 Programmable Clock 0 Register 0x48 32 read-write n CSS Master Clock Source Selection 0 3 read-write SLOW_CLK Slow Clock is selected 0x0 MAIN_CLK Main Clock is selected 0x1 PLLA_CLK PLLA Clock is selected 0x2 MCK Master Clock is selected 0x4 PRES Programmable Clock Prescaler 4 3 read-write CLK_1 Selected clock 0x0 CLK_2 Selected clock divided by 2 0x1 CLK_4 Selected clock divided by 4 0x2 CLK_8 Selected clock divided by 8 0x3 CLK_16 Selected clock divided by 16 0x4 CLK_32 Selected clock divided by 32 0x5 CLK_64 Selected clock divided by 64 0x6 PCK[0] Programmable Clock 0 Register 0x80 32 read-write n 0x0 0x0 CSS Master Clock Source Selection 0 3 read-write SLOW_CLK Slow Clock is selected 0x0 MAIN_CLK Main Clock is selected 0x1 PLLA_CLK PLLA Clock is selected 0x2 MCK Master Clock is selected 0x4 PRES Programmable Clock Prescaler 4 3 read-write CLK_1 Selected clock 0x0 CLK_2 Selected clock divided by 2 0x1 CLK_4 Selected clock divided by 4 0x2 CLK_8 Selected clock divided by 8 0x3 CLK_16 Selected clock divided by 16 0x4 CLK_32 Selected clock divided by 32 0x5 CLK_64 Selected clock divided by 64 0x6 PCK[1] Programmable Clock 0 Register 0xC4 32 read-write n 0x0 0x0 CSS Master Clock Source Selection 0 3 read-write SLOW_CLK Slow Clock is selected 0x0 MAIN_CLK Main Clock is selected 0x1 PLLA_CLK PLLA Clock is selected 0x2 MCK Master Clock is selected 0x4 PRES Programmable Clock Prescaler 4 3 read-write CLK_1 Selected clock 0x0 CLK_2 Selected clock divided by 2 0x1 CLK_4 Selected clock divided by 4 0x2 CLK_8 Selected clock divided by 8 0x3 CLK_16 Selected clock divided by 16 0x4 CLK_32 Selected clock divided by 32 0x5 CLK_64 Selected clock divided by 64 0x6 PCK[2] Programmable Clock 0 Register 0x10C 32 read-write n 0x0 0x0 CSS Master Clock Source Selection 0 3 read-write SLOW_CLK Slow Clock is selected 0x0 MAIN_CLK Main Clock is selected 0x1 PLLA_CLK PLLA Clock is selected 0x2 MCK Master Clock is selected 0x4 PRES Programmable Clock Prescaler 4 3 read-write CLK_1 Selected clock 0x0 CLK_2 Selected clock divided by 2 0x1 CLK_4 Selected clock divided by 4 0x2 CLK_8 Selected clock divided by 8 0x3 CLK_16 Selected clock divided by 16 0x4 CLK_32 Selected clock divided by 32 0x5 CLK_64 Selected clock divided by 64 0x6 PCSR0 Peripheral Clock Status Register 0 0x18 32 read-only n 0x0 0x0 PID10 Peripheral Clock 10 Status 10 1 read-only PID11 Peripheral Clock 11 Status 11 1 read-only PID12 Peripheral Clock 12 Status 12 1 read-only PID13 Peripheral Clock 13 Status 13 1 read-only PID14 Peripheral Clock 14 Status 14 1 read-only PID15 Peripheral Clock 15 Status 15 1 read-only PID16 Peripheral Clock 16 Status 16 1 read-only PID17 Peripheral Clock 17 Status 17 1 read-only PID18 Peripheral Clock 18 Status 18 1 read-only PID19 Peripheral Clock 19 Status 19 1 read-only PID20 Peripheral Clock 20 Status 20 1 read-only PID21 Peripheral Clock 21 Status 21 1 read-only PID22 Peripheral Clock 22 Status 22 1 read-only PID23 Peripheral Clock 23 Status 23 1 read-only PID24 Peripheral Clock 24 Status 24 1 read-only PID25 Peripheral Clock 25 Status 25 1 read-only PID26 Peripheral Clock 26 Status 26 1 read-only PID27 Peripheral Clock 27 Status 27 1 read-only PID28 Peripheral Clock 28 Status 28 1 read-only PID29 Peripheral Clock 29 Status 29 1 read-only PID8 Peripheral Clock 8 Status 8 1 read-only PID9 Peripheral Clock 9 Status 9 1 read-only PMMR PLL Maximum Multiplier Value Register 0x130 32 read-write n 0x0 0x0 PLLA_MMAX PLLA Maximum Allowed Multiplier Value 0 11 read-write SCDR System Clock Disable Register 0x4 32 write-only n 0x0 0x0 PCK0 Programmable Clock 0 Output Disable 8 1 write-only PCK1 Programmable Clock 1 Output Disable 9 1 write-only PCK2 Programmable Clock 2 Output Disable 10 1 write-only SCER System Clock Enable Register 0x0 32 write-only n 0x0 0x0 PCK0 Programmable Clock 0 Output Enable 8 1 write-only PCK1 Programmable Clock 1 Output Enable 9 1 write-only PCK2 Programmable Clock 2 Output Enable 10 1 write-only SCSR System Clock Status Register 0x8 32 read-only n 0x0 0x0 PCK0 Programmable Clock 0 Output Status 8 1 read-only PCK1 Programmable Clock 1 Output Status 9 1 read-only PCK2 Programmable Clock 2 Output Status 10 1 read-only SR Status Register 0x68 32 read-only n 0x0 0x0 CFDEV Clock Failure Detector Event 18 1 read-only CFDS Clock Failure Detector Status 19 1 read-only FOS Clock Failure Detector Fault Output Status 20 1 read-only LOCKA PLLA Lock Status 1 1 read-only MCKRDY Master Clock Status 3 1 read-only MOSCRCS Main On-Chip RC Oscillator Status 17 1 read-only MOSCSELS Main Oscillator Selection Status 16 1 read-only MOSCXTS Main XTAL Oscillator Status 0 1 read-only OSCSELS Slow Clock Oscillator Selection 7 1 read-only PCKRDY0 Programmable Clock Ready Status 8 1 read-only PCKRDY1 Programmable Clock Ready Status 9 1 read-only PCKRDY2 Programmable Clock Ready Status 10 1 read-only WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 0x504D43 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only RSTC Reset Controller SYSC 0x0 0x0 0x200 registers n CR Control Register 0x0 32 write-only n 0x0 0x0 EXTRST External Reset 3 1 write-only KEY System Reset Key 24 8 write-only PASSWD Writing any other value in this field aborts the write operation. 0xA5 PERRST Peripheral Reset 2 1 write-only PROCRST Processor Reset 0 1 write-only MR Mode Register 0x8 32 read-write n 0x0 0x0 ERSTL External Reset Length 8 4 read-write KEY Write Access Password 24 8 read-write PASSWD Writing any other value in this field aborts the write operation.Always reads as 0. 0xA5 URSTEN User Reset Enable 0 1 read-write URSTIEN User Reset Interrupt Enable 4 1 read-write SR Status Register 0x4 32 read-only n 0x0 0x0 NRSTL NRST Pin Level 16 1 read-only RSTTYP Reset Type 8 3 read-only GENERAL_RST First power-up Reset 0x0 BACKUP_RST Return from Backup Mode 0x1 WDT_RST Watchdog fault occurred 0x2 SOFT_RST Processor reset required by the software 0x3 USER_RST NRST pin detected low 0x4 SRCMP Software Reset Command in Progress 17 1 read-only URSTS User Reset Status 0 1 read-only RTC Real-time Clock SYSC 0x0 0x0 0x200 registers n CALALR Calendar Alarm Register 0x14 32 read-write n 0x0 0x0 DATE Date Alarm 24 6 read-write DATEEN Date Alarm Enable 31 1 read-write MONTH Month Alarm 16 5 read-write MTHEN Month Alarm Enable 23 1 read-write CALR Calendar Register 0xC 32 read-write n 0x0 0x0 CENT Current Century 0 7 read-write DATE Current Day in Current Month 24 6 read-write DAY Current Day in Current Week 21 3 read-write MONTH Current Month 16 5 read-write YEAR Current Year 8 8 read-write CR Control Register 0x0 32 read-write n 0x0 0x0 CALEVSEL Calendar Event Selection 16 2 read-write WEEK Week change (every Monday at time 00:00:00) 0x0 MONTH Month change (every 01 of each month at time 00:00:00) 0x1 YEAR Year change (every January 1 at time 00:00:00) 0x2 TIMEVSEL Time Event Selection 8 2 read-write MINUTE Minute change 0x0 HOUR Hour change 0x1 MIDNIGHT Every day at midnight 0x2 NOON Every day at noon 0x3 UPDCAL Update Request Calendar Register 1 1 read-write UPDTIM Update Request Time Register 0 1 read-write IDR Interrupt Disable Register 0x24 32 write-only n 0x0 0x0 ACKDIS Acknowledge Update Interrupt Disable 0 1 write-only ALRDIS Alarm Interrupt Disable 1 1 write-only CALDIS Calendar Event Interrupt Disable 4 1 write-only SECDIS Second Event Interrupt Disable 2 1 write-only TDERRDIS Time and/or Date Error Interrupt Disable 5 1 write-only TIMDIS Time Event Interrupt Disable 3 1 write-only IER Interrupt Enable Register 0x20 32 write-only n 0x0 0x0 ACKEN Acknowledge Update Interrupt Enable 0 1 write-only ALREN Alarm Interrupt Enable 1 1 write-only CALEN Calendar Event Interrupt Enable 4 1 write-only SECEN Second Event Interrupt Enable 2 1 write-only TDERREN Time and/or Date Error Interrupt Enable 5 1 write-only TIMEN Time Event Interrupt Enable 3 1 write-only IMR Interrupt Mask Register 0x28 32 read-only n 0x0 0x0 ACK Acknowledge Update Interrupt Mask 0 1 read-only ALR Alarm Interrupt Mask 1 1 read-only CAL Calendar Event Interrupt Mask 4 1 read-only SEC Second Event Interrupt Mask 2 1 read-only TIM Time Event Interrupt Mask 3 1 read-only MR Mode Register 0x4 32 read-write n 0x0 0x0 CORRECTION Slow Clock Correction 8 7 read-write HIGHPPM HIGH PPM Correction 15 1 read-write HRMOD 12-/24-hour Mode 0 1 read-write NEGPPM NEGative PPM Correction 4 1 read-write OUT0 All ADC Channel Trigger Event Source Selection 16 3 read-write NO_WAVE no waveform, stuck at '0' 0x0 FREQ1HZ 1 Hz square wave 0x1 FREQ32HZ 32 Hz square wave 0x2 FREQ64HZ 64 Hz square wave 0x3 FREQ512HZ 512 Hz square wave 0x4 ALARM_FLAG output is a copy of the alarm flag 0x6 OUT1 ADC Last Channel Trigger Event Source Selection 20 3 read-write NO_WAVE no waveform, stuck at '0' 0x0 FREQ1HZ 1 Hz square wave 0x1 FREQ32HZ 32 Hz square wave 0x2 FREQ64HZ 64 Hz square wave 0x3 FREQ512HZ 512 Hz square wave 0x4 ALARM_FLAG output is a copy of the alarm flag 0x6 PERSIAN PERSIAN Calendar 1 1 read-write SCCR Status Clear Command Register 0x1C 32 write-only n 0x0 0x0 ACKCLR Acknowledge Clear 0 1 write-only ALRCLR Alarm Clear 1 1 write-only CALCLR Calendar Clear 4 1 write-only SECCLR Second Clear 2 1 write-only TDERRCLR Time and/or Date Free Running Error Clear 5 1 write-only TIMCLR Time Clear 3 1 write-only SR Status Register 0x18 32 read-only n 0x0 0x0 ACKUPD Acknowledge for Update 0 1 read-only FREERUN Time and calendar registers cannot be updated. 0 UPDATE Time and calendar registers can be updated. 1 ALARM Alarm Flag 1 1 read-only NO_ALARMEVENT No alarm matching condition occurred. 0 ALARMEVENT An alarm matching condition has occurred. 1 CALEV Calendar Event 4 1 read-only NO_CALEVENT No calendar event has occurred since the last clear. 0 CALEVENT At least one calendar event has occurred since the last clear. 1 SEC Second Event 2 1 read-only NO_SECEVENT No second event has occurred since the last clear. 0 SECEVENT At least one second event has occurred since the last clear. 1 TDERR Time and/or Date Free Running Error 5 1 read-only CORRECT The internal free running counters are carrying valid values since the last read of the Status Register (RTC_SR). 0 ERR_TIMEDATE The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. 1 TIMEV Time Event 3 1 read-only NO_TIMEVENT No time event has occurred since the last clear. 0 TIMEVENT At least one time event has occurred since the last clear. 1 TIMALR Time Alarm Register 0x10 32 read-write n 0x0 0x0 AMPM AM/PM Indicator 22 1 read-write HOUR Hour Alarm 16 6 read-write HOUREN Hour Alarm Enable 23 1 read-write MIN Minute Alarm 8 7 read-write MINEN Minute Alarm Enable 15 1 read-write SEC Second Alarm 0 7 read-write SECEN Second Alarm Enable 7 1 read-write TIMR Time Register 0x8 32 read-write n 0x0 0x0 AMPM Ante Meridiem Post Meridiem Indicator 22 1 read-write HOUR Current Hour 16 6 read-write MIN Current Minute 8 7 read-write SEC Current Second 0 7 read-write VER Valid Entry Register 0x2C 32 read-only n 0x0 0x0 NVCAL Non-valid Calendar 1 1 read-only NVCALALR Non-valid Calendar Alarm 3 1 read-only NVTIM Non-valid Time 0 1 read-only NVTIMALR Non-valid Time Alarm 2 1 read-only RTT Real-time Timer SYSC 0x0 0x0 0x200 registers n AR Alarm Register 0x4 32 read-write n 0x0 0x0 ALMV Alarm Value 0 32 read-write MR Mode Register 0x0 32 read-write n 0x0 0x0 ALMIEN Alarm Interrupt Enable 16 1 read-write RTC1HZ Real-Time Clock 1 Hz Clock Selection 24 1 read-write RTPRES Real-time Timer Prescaler Value 0 16 read-write RTTDIS Real-time Timer Disable 20 1 read-write RTTINCIEN Real-time Timer Increment Interrupt Enable 17 1 read-write RTTRST Real-time Timer Restart 18 1 read-write SR Status Register 0xC 32 read-only n 0x0 0x0 ALMS Real-time Alarm Status 0 1 read-only RTTINC Prescaler Roll-over Status 1 1 read-only VR Value Register 0x8 32 read-only n 0x0 0x0 CRTV Current Real-time Value 0 32 read-only SPI Serial Peripheral Interface SPI 0x0 0x0 0x50 registers n SPI 21 CR Control Register 0x0 32 write-only n 0x0 0x0 LASTXFER Last Transfer 24 1 write-only SPIDIS SPI Disable 1 1 write-only SPIEN SPI Enable 0 1 write-only SWRST SPI Software Reset 7 1 write-only CSR0 Chip Select Register 0x30 32 read-write n BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Baud Rate 8 8 read-write CSR1 Chip Select Register 0x34 32 read-write n BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Baud Rate 8 8 read-write CSR2 Chip Select Register 0x38 32 read-write n BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Baud Rate 8 8 read-write CSR3 Chip Select Register 0x3C 32 read-write n BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Baud Rate 8 8 read-write CSR[0] Chip Select Register 0x60 32 read-write n 0x0 0x0 BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Baud Rate 8 8 read-write CSR[1] Chip Select Register 0x94 32 read-write n 0x0 0x0 BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Baud Rate 8 8 read-write CSR[2] Chip Select Register 0xCC 32 read-write n 0x0 0x0 BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Baud Rate 8 8 read-write CSR[3] Chip Select Register 0x108 32 read-write n 0x0 0x0 BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Baud Rate 8 8 read-write IDR Interrupt Disable Register 0x18 32 write-only n 0x0 0x0 ENDRX End of Receive Buffer Interrupt Disable 4 1 write-only ENDTX End of Transmit Buffer Interrupt Disable 5 1 write-only MODF Mode Fault Error Interrupt Disable 2 1 write-only NSSR NSS Rising Interrupt Disable 8 1 write-only OVRES Overrun Error Interrupt Disable 3 1 write-only RDRF Receive Data Register Full Interrupt Disable 0 1 write-only RXBUFF Receive Buffer Full Interrupt Disable 6 1 write-only TDRE SPI Transmit Data Register Empty Interrupt Disable 1 1 write-only TXBUFE Transmit Buffer Empty Interrupt Disable 7 1 write-only TXEMPTY Transmission Registers Empty Disable 9 1 write-only UNDES Underrun Error Interrupt Disable 10 1 write-only IER Interrupt Enable Register 0x14 32 write-only n 0x0 0x0 ENDRX End of Receive Buffer Interrupt Enable 4 1 write-only ENDTX End of Transmit Buffer Interrupt Enable 5 1 write-only MODF Mode Fault Error Interrupt Enable 2 1 write-only NSSR NSS Rising Interrupt Enable 8 1 write-only OVRES Overrun Error Interrupt Enable 3 1 write-only RDRF Receive Data Register Full Interrupt Enable 0 1 write-only RXBUFF Receive Buffer Full Interrupt Enable 6 1 write-only TDRE SPI Transmit Data Register Empty Interrupt Enable 1 1 write-only TXBUFE Transmit Buffer Empty Interrupt Enable 7 1 write-only TXEMPTY Transmission Registers Empty Enable 9 1 write-only UNDES Underrun Error Interrupt Enable 10 1 write-only IMR Interrupt Mask Register 0x1C 32 read-only n 0x0 0x0 ENDRX End of Receive Buffer Interrupt Mask 4 1 read-only ENDTX End of Transmit Buffer Interrupt Mask 5 1 read-only MODF Mode Fault Error Interrupt Mask 2 1 read-only NSSR NSS Rising Interrupt Mask 8 1 read-only OVRES Overrun Error Interrupt Mask 3 1 read-only RDRF Receive Data Register Full Interrupt Mask 0 1 read-only RXBUFF Receive Buffer Full Interrupt Mask 6 1 read-only TDRE SPI Transmit Data Register Empty Interrupt Mask 1 1 read-only TXBUFE Transmit Buffer Empty Interrupt Mask 7 1 read-only TXEMPTY Transmission Registers Empty Mask 9 1 read-only UNDES Underrun Error Interrupt Mask 10 1 read-only MR Mode Register 0x4 32 read-write n 0x0 0x0 DLYBCS Delay Between Chip Selects 24 8 read-write LLB Local Loopback Enable 7 1 read-write MODFDIS Mode Fault Detection 4 1 read-write MSTR Master/Slave Mode 0 1 read-write PCS Peripheral Chip Select 16 4 read-write PCSDEC Chip Select Decode 2 1 read-write PS Peripheral Select 1 1 read-write WDRBT Wait Data Read Before Transfer 5 1 read-write PTCR Transfer Control Register 0x120 32 write-only n 0x0 0x0 RXTDIS Receiver Transfer Disable 1 1 write-only RXTEN Receiver Transfer Enable 0 1 write-only TXTDIS Transmitter Transfer Disable 9 1 write-only TXTEN Transmitter Transfer Enable 8 1 write-only PTSR Transfer Status Register 0x124 32 read-only n 0x0 0x0 RXTEN Receiver Transfer Enable 0 1 read-only TXTEN Transmitter Transfer Enable 8 1 read-only RCR Receive Counter Register 0x104 32 read-write n 0x0 0x0 RXCTR Receive Counter Register 0 16 read-write RDR Receive Data Register 0x8 32 read-only n 0x0 0x0 PCS Peripheral Chip Select 16 4 read-only RD Receive Data 0 16 read-only RNCR Receive Next Counter Register 0x114 32 read-write n 0x0 0x0 RXNCTR Receive Next Counter 0 16 read-write RNPR Receive Next Pointer Register 0x110 32 read-write n 0x0 0x0 RXNPTR Receive Next Pointer 0 32 read-write RPR Receive Pointer Register 0x100 32 read-write n 0x0 0x0 RXPTR Receive Pointer Register 0 32 read-write SR Status Register 0x10 32 read-only n 0x0 0x0 ENDRX End of RX buffer 4 1 read-only ENDTX End of TX buffer 5 1 read-only MODF Mode Fault Error 2 1 read-only NSSR NSS Rising 8 1 read-only OVRES Overrun Error Status 3 1 read-only RDRF Receive Data Register Full 0 1 read-only RXBUFF RX Buffer Full 6 1 read-only SPIENS SPI Enable Status 16 1 read-only TDRE Transmit Data Register Empty 1 1 read-only TXBUFE TX Buffer Empty 7 1 read-only TXEMPTY Transmission Registers Empty 9 1 read-only UNDES Underrun Error Status (Slave Mode Only) 10 1 read-only TCR Transmit Counter Register 0x10C 32 read-write n 0x0 0x0 TXCTR Transmit Counter Register 0 16 read-write TDR Transmit Data Register 0xC 32 write-only n 0x0 0x0 LASTXFER Last Transfer 24 1 write-only PCS Peripheral Chip Select 16 4 write-only TD Transmit Data 0 16 write-only TNCR Transmit Next Counter Register 0x11C 32 read-write n 0x0 0x0 TXNCTR Transmit Counter Next 0 16 read-write TNPR Transmit Next Pointer Register 0x118 32 read-write n 0x0 0x0 TXNPTR Transmit Next Pointer 0 32 read-write TPR Transmit Pointer Register 0x108 32 read-write n 0x0 0x0 TXPTR Transmit Counter Register 0 32 read-write WPMR Write Protection Control Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protect Enable 0 1 read-write WPKEY Write Protect Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x535049 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 8 read-only SUPC Supply Controller SYSC 0x0 0x0 0x200 registers n CR Supply Controller Control Register 0x0 32 write-only n 0x0 0x0 KEY Password 24 8 write-only PASSWD Writing any other value in this field aborts the write operation.Always reads as 0. 0xA5 XTALSEL Crystal Oscillator Select 3 1 write-only NO_EFFECT No effect. 0 CRYSTAL_SEL If KEY is correct, switches the slow clock on the crystal oscillator output. 1 ZERO Zero 2 1 write-only MR Supply Controller Mode Register 0x8 32 read-write n 0x0 0x0 BODDIS POR Core Disable 13 1 read-write ENABLE The core brownout detector is enabled. 0 DISABLE The core brownout detector is disabled. 1 BODRSTEN POR Core Reset Enable 12 1 read-write NOT_ENABLE The core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. 0 ENABLE The core reset signal, vddcore_nreset is asserted when a brownout detection occurs. 1 KEY Password Key 24 8 read-write PASSWD Writing any other value in this field aborts the write operation.Always reads as 0. 0xA5 OSCBYPASS Oscillator Bypass 20 1 read-write NO_EFFECT No effect. Clock selection depends on XTALSEL value. 0 BYPASS The 32 kHz crystal oscillator is selected and put in bypass mode. 1 SMMR Supply Controller Supply Monitor Mode Register 0x4 32 read-write n 0x0 0x0 SMIEN Supply Monitor Interrupt Enable 13 1 read-write NOT_ENABLE The SUPC interrupt signal is not affected when a supply monitor detection occurs. 0 ENABLE The SUPC interrupt signal is asserted when a supply monitor detection occurs. 1 SMRSTEN Supply Monitor Reset Enable 12 1 read-write NOT_ENABLE The core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. 0 ENABLE The core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. 1 SMSMPL Supply Monitor Sampling Period 8 3 read-write SMD Supply Monitor disabled 0x0 CSM Continuous Supply Monitor 0x1 32SLCK Supply Monitor enables one SLCK period every 32 SLCK periods 0x2 256SLCK Supply Monitor enables one SLCK period every 256 SLCK periods 0x3 2048SLCK Supply Monitor enables one SLCK period every 2,048 SLCK periods 0x4 SMTH Supply Monitor Threshold 0 4 read-write SR Supply Controller Status Register 0x14 32 read-only n 0x0 0x0 BODRSTS Brownout Detector Reset Status 3 1 read-only NO No core brownout rising edge event has been detected since the last read of the SUPC_SR. 0 PRESENT At least one brownout output rising edge event has been detected since the last read of the SUPC_SR. 1 OSCSEL 32-kHz Oscillator Selection Status 7 1 read-only RC The slow clock, SLCK is generated by the embedded 32 kHz RC oscillator. 0 CRYST The slow clock, SLCK is generated by the 32 kHz crystal oscillator. 1 SMOS Supply Monitor Output Status 6 1 read-only HIGH The supply monitor detected VDDIO higher than its threshold at its last measurement. 0 LOW The supply monitor detected VDDIO lower than its threshold at its last measurement. 1 SMRSTS Supply Monitor Reset Status 4 1 read-only NO No supply monitor detection has generated a core reset since the last read of the SUPC_SR. 0 PRESENT At least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. 1 SMS Supply Monitor Status 5 1 read-only NO No supply monitor detection since the last read of SUPC_SR. 0 PRESENT At least one supply monitor detection since the last read of SUPC_SR. 1 TC0 Timer Counter 0 TC 0x0 0x0 0x50 registers n TC0 23 TC1 24 TC2 25 BCR Block Control Register 0xC0 32 write-only n 0x0 0x0 SYNC Synchro Command 0 1 write-only BMR Block Mode Register 0xC4 32 read-write n 0x0 0x0 TC0XC0S External Clock Signal 0 Selection 0 2 read-write TCLK0 Signal connected to XC0: TCLK0 0x0 TIOA1 Signal connected to XC0: TIOA1 0x2 TIOA2 Signal connected to XC0: TIOA2 0x3 TC1XC1S External Clock Signal 1 Selection 2 2 read-write TCLK1 Signal connected to XC1: TCLK1 0x0 TIOA0 Signal connected to XC1: TIOA0 0x2 TIOA2 Signal connected to XC1: TIOA2 0x3 TC2XC2S External Clock Signal 2 Selection 4 2 read-write TCLK2 Signal connected to XC2: TCLK2 0x0 TIOA0 Signal connected to XC2: TIOA0 0x2 TIOA1 Signal connected to XC2: TIOA1 0x3 CCR0 Channel Control Register (channel = 0) 0x0 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 write-only CLKEN Counter Clock Enable Command 0 1 write-only SWTRG Software Trigger Command 2 1 write-only CCR1 Channel Control Register (channel = 1) 0x40 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 write-only CLKEN Counter Clock Enable Command 0 1 write-only SWTRG Software Trigger Command 2 1 write-only CCR2 Channel Control Register (channel = 2) 0x80 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 write-only CLKEN Counter Clock Enable Command 0 1 write-only SWTRG Software Trigger Command 2 1 write-only CMR0 Channel Mode Register (channel = 0) 0x4 32 read-write n 0x0 0x0 ABETRG TIOA or TIOB External Trigger Selection 10 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 read-write LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDRA RA Loading Edge Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 LDRB RB Loading Edge Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 SBSMPLR Loading Edge Subsampling Ratio 20 3 read-write ONE Load a Capture Register each selected edge 0x0 HALF Load a Capture Register every 2 selected edges 0x1 FOURTH Load a Capture Register every 4 selected edges 0x2 EIGHTH Load a Capture Register every 8 selected edges 0x3 SIXTEENTH Load a Capture Register every 16 selected edges 0x4 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal TIMER_CLOCK1 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal TIMER_CLOCK2 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal TIMER_CLOCK3 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal TIMER_CLOCK4 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal TIMER_CLOCK5 clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write CMR0_WAVE_EQ_1 Channel Mode Register (channel = 0) WAVE_EQ_1 0x4 32 read-write n 0x0 0x0 ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ENETRG External Event Trigger Enable 12 1 read-write TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal TIMER_CLOCK1 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal TIMER_CLOCK2 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal TIMER_CLOCK3 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal TIMER_CLOCK4 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal TIMER_CLOCK5 clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 CMR1 Channel Mode Register (channel = 1) 0x44 32 read-write n 0x0 0x0 ABETRG TIOA or TIOB External Trigger Selection 10 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 read-write LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDRA RA Loading Edge Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 LDRB RB Loading Edge Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 SBSMPLR Loading Edge Subsampling Ratio 20 3 read-write ONE Load a Capture Register each selected edge 0x0 HALF Load a Capture Register every 2 selected edges 0x1 FOURTH Load a Capture Register every 4 selected edges 0x2 EIGHTH Load a Capture Register every 8 selected edges 0x3 SIXTEENTH Load a Capture Register every 16 selected edges 0x4 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal TIMER_CLOCK1 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal TIMER_CLOCK2 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal TIMER_CLOCK3 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal TIMER_CLOCK4 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal TIMER_CLOCK5 clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write CMR1_WAVE_EQ_1 Channel Mode Register (channel = 1) WAVE_EQ_1 0x44 32 read-write n 0x0 0x0 ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ENETRG External Event Trigger Enable 12 1 read-write TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal TIMER_CLOCK1 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal TIMER_CLOCK2 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal TIMER_CLOCK3 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal TIMER_CLOCK4 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal TIMER_CLOCK5 clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 CMR2 Channel Mode Register (channel = 2) 0x84 32 read-write n 0x0 0x0 ABETRG TIOA or TIOB External Trigger Selection 10 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 read-write LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDRA RA Loading Edge Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 LDRB RB Loading Edge Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 SBSMPLR Loading Edge Subsampling Ratio 20 3 read-write ONE Load a Capture Register each selected edge 0x0 HALF Load a Capture Register every 2 selected edges 0x1 FOURTH Load a Capture Register every 4 selected edges 0x2 EIGHTH Load a Capture Register every 8 selected edges 0x3 SIXTEENTH Load a Capture Register every 16 selected edges 0x4 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal TIMER_CLOCK1 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal TIMER_CLOCK2 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal TIMER_CLOCK3 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal TIMER_CLOCK4 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal TIMER_CLOCK5 clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write CMR2_WAVE_EQ_1 Channel Mode Register (channel = 2) WAVE_EQ_1 0x84 32 read-write n 0x0 0x0 ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ENETRG External Event Trigger Enable 12 1 read-write TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal TIMER_CLOCK1 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal TIMER_CLOCK2 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal TIMER_CLOCK3 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal TIMER_CLOCK4 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal TIMER_CLOCK5 clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 CV0 Counter Value (channel = 0) 0x10 32 read-only n 0x0 0x0 CV Counter Value 0 32 read-only CV1 Counter Value (channel = 1) 0x50 32 read-only n 0x0 0x0 CV Counter Value 0 32 read-only CV2 Counter Value (channel = 2) 0x90 32 read-only n 0x0 0x0 CV Counter Value 0 32 read-only IDR0 Interrupt Disable Register (channel = 0) 0x28 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ENDRX End of Receiver Transfer 8 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only RXBUFF Reception Buffer Full 9 1 write-only IDR1 Interrupt Disable Register (channel = 1) 0x68 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ENDRX End of Receiver Transfer 8 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only RXBUFF Reception Buffer Full 9 1 write-only IDR2 Interrupt Disable Register (channel = 2) 0xA8 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ENDRX End of Receiver Transfer 8 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only RXBUFF Reception Buffer Full 9 1 write-only IER0 Interrupt Enable Register (channel = 0) 0x24 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ENDRX End of Receiver Transfer 8 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only RXBUFF Reception Buffer Full 9 1 write-only IER1 Interrupt Enable Register (channel = 1) 0x64 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ENDRX End of Receiver Transfer 8 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only RXBUFF Reception Buffer Full 9 1 write-only IER2 Interrupt Enable Register (channel = 2) 0xA4 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ENDRX End of Receiver Transfer 8 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only RXBUFF Reception Buffer Full 9 1 write-only IMR0 Interrupt Mask Register (channel = 0) 0x2C 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only ENDRX End of Receiver Transfer 8 1 read-only ETRGS External Trigger 7 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only LOVRS Load Overrun 1 1 read-only RXBUFF Reception Buffer Full 9 1 read-only IMR1 Interrupt Mask Register (channel = 1) 0x6C 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only ENDRX End of Receiver Transfer 8 1 read-only ETRGS External Trigger 7 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only LOVRS Load Overrun 1 1 read-only RXBUFF Reception Buffer Full 9 1 read-only IMR2 Interrupt Mask Register (channel = 2) 0xAC 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only ENDRX End of Receiver Transfer 8 1 read-only ETRGS External Trigger 7 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only LOVRS Load Overrun 1 1 read-only RXBUFF Reception Buffer Full 9 1 read-only PTCR2 Transfer Control Register (pdc = 2) 0x1A0 32 write-only n 0x0 0x0 RXTDIS Receiver Transfer Disable 1 1 write-only RXTEN Receiver Transfer Enable 0 1 write-only TXTDIS Transmitter Transfer Disable 9 1 write-only TXTEN Transmitter Transfer Enable 8 1 write-only PTSR2 Transfer Status Register (pdc = 2) 0x1A4 32 read-only n 0x0 0x0 RXTEN Receiver Transfer Enable 0 1 read-only TXTEN Transmitter Transfer Enable 8 1 read-only RA0 Register A (channel = 0) 0x14 32 read-write n 0x0 0x0 RA Register A 0 32 read-write RA1 Register A (channel = 1) 0x54 32 read-write n 0x0 0x0 RA Register A 0 32 read-write RA2 Register A (channel = 2) 0x94 32 read-write n 0x0 0x0 RA Register A 0 32 read-write RB0 Register B (channel = 0) 0x18 32 read-write n 0x0 0x0 RB Register B 0 32 read-write RB1 Register B (channel = 1) 0x58 32 read-write n 0x0 0x0 RB Register B 0 32 read-write RB2 Register B (channel = 2) 0x98 32 read-write n 0x0 0x0 RB Register B 0 32 read-write RC0 Register C (channel = 0) 0x1C 32 read-write n 0x0 0x0 RC Register C 0 32 read-write RC1 Register C (channel = 1) 0x5C 32 read-write n 0x0 0x0 RC Register C 0 32 read-write RC2 Register C (channel = 2) 0x9C 32 read-write n 0x0 0x0 RC Register C 0 32 read-write RCR2 Receive Counter Register (pdc = 2) 0x184 32 read-write n 0x0 0x0 RXCTR Receive Counter Register 0 16 read-write RNCR2 Receive Next Counter Register (pdc = 2) 0x194 32 read-write n 0x0 0x0 RXNCTR Receive Next Counter 0 16 read-write RNPR2 Receive Next Pointer Register (pdc = 2) 0x190 32 read-write n 0x0 0x0 RXNPTR Receive Next Pointer 0 32 read-write RPR2 Receive Pointer Register (pdc = 2) 0x180 32 read-write n 0x0 0x0 RXPTR Receive Pointer Register 0 32 read-write SMMR0 Stepper Motor Mode Register (channel = 0) 0x8 32 read-write n 0x0 0x0 DOWN DOWN Count 1 1 read-write GCEN Gray Count Enable 0 1 read-write SMMR1 Stepper Motor Mode Register (channel = 1) 0x48 32 read-write n 0x0 0x0 DOWN DOWN Count 1 1 read-write GCEN Gray Count Enable 0 1 read-write SMMR2 Stepper Motor Mode Register (channel = 2) 0x88 32 read-write n 0x0 0x0 DOWN DOWN Count 1 1 read-write GCEN Gray Count Enable 0 1 read-write SR0 Status Register (channel = 0) 0x20 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 read-only COVFS Counter Overflow Status 0 1 read-only CPAS RA Compare Status 2 1 read-only CPBS RB Compare Status 3 1 read-only CPCS RC Compare Status 4 1 read-only ENDRX End of Receiver Transfer 8 1 read-only ETRGS External Trigger Status 7 1 read-only LDRAS RA Loading Status 5 1 read-only LDRBS RB Loading Status 6 1 read-only LOVRS Load Overrun Status 1 1 read-only MTIOA TIOA Mirror 17 1 read-only MTIOB TIOB Mirror 18 1 read-only RXBUFF Reception Buffer Full 9 1 read-only SR1 Status Register (channel = 1) 0x60 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 read-only COVFS Counter Overflow Status 0 1 read-only CPAS RA Compare Status 2 1 read-only CPBS RB Compare Status 3 1 read-only CPCS RC Compare Status 4 1 read-only ENDRX End of Receiver Transfer 8 1 read-only ETRGS External Trigger Status 7 1 read-only LDRAS RA Loading Status 5 1 read-only LDRBS RB Loading Status 6 1 read-only LOVRS Load Overrun Status 1 1 read-only MTIOA TIOA Mirror 17 1 read-only MTIOB TIOB Mirror 18 1 read-only RXBUFF Reception Buffer Full 9 1 read-only SR2 Status Register (channel = 2) 0xA0 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 read-only COVFS Counter Overflow Status 0 1 read-only CPAS RA Compare Status 2 1 read-only CPBS RB Compare Status 3 1 read-only CPCS RC Compare Status 4 1 read-only ENDRX End of Receiver Transfer 8 1 read-only ETRGS External Trigger Status 7 1 read-only LDRAS RA Loading Status 5 1 read-only LDRBS RB Loading Status 6 1 read-only LOVRS Load Overrun Status 1 1 read-only MTIOA TIOA Mirror 17 1 read-only MTIOB TIOB Mirror 18 1 read-only RXBUFF Reception Buffer Full 9 1 read-only WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protect Enable 0 1 read-write WPKEY Write Protect KEY 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x54494D TWI0 Two-wire Interface High Speed TWIHS 0x0 0x0 0x50 registers n TWI0 19 ACR Alternative Command Register 0x40 32 read-write n 0x0 0x0 CR Control Register 0x0 32 write-only n 0x0 0x0 CLEAR Bus CLEAR Command 15 1 write-only HSDIS TWI High-Speed Mode Disabled 9 1 write-only HSEN TWI High-Speed Mode Enabled 8 1 write-only MSDIS TWI Master Mode Disabled 3 1 write-only MSEN TWI Master Mode Enabled 2 1 write-only PECDIS Packet Error Checking Disable 13 1 write-only PECEN Packet Error Checking Enable 12 1 write-only PECRQ PEC Request 14 1 write-only QUICK SMBUS Quick Command 6 1 write-only SMBDIS SMBus Mode Disabled 11 1 write-only SMBEN SMBus Mode Enabled 10 1 write-only START Send a START Condition 0 1 write-only STOP Send a STOP Condition 1 1 write-only SVDIS TWI Slave Mode Disabled 5 1 write-only SVEN TWI Slave Mode Enabled 4 1 write-only SWRST Software Reset 7 1 write-only CWGR Clock Waveform Generator Register 0x10 32 read-write n 0x0 0x0 CHDIV Clock High Divider 8 8 read-write CKDIV Clock Divider 16 3 read-write CLDIV Clock Low Divider 0 8 read-write HOLD TWD Hold Time Versus TWCK Falling 24 5 read-write FILTR Filter Register 0x44 32 read-write n 0x0 0x0 FILT RX Digital Filter 0 1 read-write PADFCFG PAD Filter Config 2 1 read-write PADFEN PAD Filter Enable 1 1 read-write THRES Digital Filter Threshold 8 3 read-write IADR Internal Address Register 0xC 32 read-write n 0x0 0x0 IADR Internal Address 0 24 read-write IDR Interrupt Disable Register 0x28 32 write-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Disable 9 1 write-only ENDRX End of Receive Buffer Interrupt Disable 12 1 write-only ENDTX End of Transmit Buffer Interrupt Disable 13 1 write-only EOSACC End Of Slave Access Interrupt Disable 11 1 write-only GACC General Call Access Interrupt Disable 5 1 write-only MCACK Master Code Acknowledge Interrupt Disable 16 1 write-only NACK Not Acknowledge Interrupt Disable 8 1 write-only OVRE Overrun Error Interrupt Disable 6 1 write-only PECERR PEC Error Interrupt Disable 19 1 write-only RXBUFF Receive Buffer Full Interrupt Disable 14 1 write-only RXRDY Receive Holding Register Ready Interrupt Disable 1 1 write-only SCL_WS Clock Wait State Interrupt Disable 10 1 write-only SMBDAM SMBus Default Address Match Interrupt Disable 20 1 write-only SMBHHM SMBus Host Header Address Match Interrupt Disable 21 1 write-only SVACC Slave Access Interrupt Disable 4 1 write-only TOUT Timeout Error Interrupt Disable 18 1 write-only TXBUFE Transmit Buffer Empty Interrupt Disable 15 1 write-only TXCOMP Transmission Completed Interrupt Disable 0 1 write-only TXRDY Transmit Holding Register Ready Interrupt Disable 2 1 write-only UNRE Underrun Error Interrupt Disable 7 1 write-only IER Interrupt Enable Register 0x24 32 write-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Enable 9 1 write-only ENDRX End of Receive Buffer Interrupt Enable 12 1 write-only ENDTX End of Transmit Buffer Interrupt Enable 13 1 write-only EOSACC End Of Slave Access Interrupt Enable 11 1 write-only GACC General Call Access Interrupt Enable 5 1 write-only MCACK Master Code Acknowledge Interrupt Enable 16 1 write-only NACK Not Acknowledge Interrupt Enable 8 1 write-only OVRE Overrun Error Interrupt Enable 6 1 write-only PECERR PEC Error Interrupt Enable 19 1 write-only RXBUFF Receive Buffer Full Interrupt Enable 14 1 write-only RXRDY Receive Holding Register Ready Interrupt Enable 1 1 write-only SCL_WS Clock Wait State Interrupt Enable 10 1 write-only SMBDAM SMBus Default Address Match Interrupt Enable 20 1 write-only SMBHHM SMBus Host Header Address Match Interrupt Enable 21 1 write-only SVACC Slave Access Interrupt Enable 4 1 write-only TOUT Timeout Error Interrupt Enable 18 1 write-only TXBUFE Transmit Buffer Empty Interrupt Enable 15 1 write-only TXCOMP Transmission Completed Interrupt Enable 0 1 write-only TXRDY Transmit Holding Register Ready Interrupt Enable 2 1 write-only UNRE Underrun Error Interrupt Enable 7 1 write-only IMR Interrupt Mask Register 0x2C 32 read-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Mask 9 1 read-only ENDRX End of Receive Buffer Interrupt Mask 12 1 read-only ENDTX End of Transmit Buffer Interrupt Mask 13 1 read-only EOSACC End Of Slave Access Interrupt Mask 11 1 read-only GACC General Call Access Interrupt Mask 5 1 read-only MCACK Master Code Acknowledge Interrupt Mask 16 1 read-only NACK Not Acknowledge Interrupt Mask 8 1 read-only OVRE Overrun Error Interrupt Mask 6 1 read-only PECERR PEC Error Interrupt Mask 19 1 read-only RXBUFF Receive Buffer Full Interrupt Mask 14 1 read-only RXRDY Receive Holding Register Ready Interrupt Mask 1 1 read-only SCL_WS Clock Wait State Interrupt Mask 10 1 read-only SMBDAM SMBus Default Address Match Interrupt Mask 20 1 read-only SMBHHM SMBus Host Header Address Match Interrupt Mask 21 1 read-only SVACC Slave Access Interrupt Mask 4 1 read-only TOUT Timeout Error Interrupt Mask 18 1 read-only TXBUFE Transmit Buffer Empty Interrupt Mask 15 1 read-only TXCOMP Transmission Completed Interrupt Mask 0 1 read-only TXRDY Transmit Holding Register Ready Interrupt Mask 2 1 read-only UNRE Underrun Error Interrupt Mask 7 1 read-only MMR Master Mode Register 0x4 32 read-write n 0x0 0x0 DADR Device Address 16 7 read-write IADRSZ Internal Device Address Size 8 2 read-write NONE No internal device address 0x0 1_BYTE One-byte internal device address 0x1 2_BYTE Two-byte internal device address 0x2 3_BYTE Three-byte internal device address 0x3 MREAD Master Read Direction 12 1 read-write PTCR Transfer Control Register 0x120 32 write-only n 0x0 0x0 RXTDIS Receiver Transfer Disable 1 1 write-only RXTEN Receiver Transfer Enable 0 1 write-only TXTDIS Transmitter Transfer Disable 9 1 write-only TXTEN Transmitter Transfer Enable 8 1 write-only PTSR Transfer Status Register 0x124 32 read-only n 0x0 0x0 RXTEN Receiver Transfer Enable 0 1 read-only TXTEN Transmitter Transfer Enable 8 1 read-only RCR Receive Counter Register 0x104 32 read-write n 0x0 0x0 RXCTR Receive Counter Register 0 16 read-write RHR Receive Holding Register 0x30 32 read-only n 0x0 0x0 RXDATA Master or Slave Receive Holding Data 0 8 read-only RNCR Receive Next Counter Register 0x114 32 read-write n 0x0 0x0 RXNCTR Receive Next Counter 0 16 read-write RNPR Receive Next Pointer Register 0x110 32 read-write n 0x0 0x0 RXNPTR Receive Next Pointer 0 32 read-write RPR Receive Pointer Register 0x100 32 read-write n 0x0 0x0 RXPTR Receive Pointer Register 0 32 read-write SMBTR SMBus Timing Register 0x38 32 read-write n 0x0 0x0 PRESC SMBus Clock Prescaler 0 4 read-write THMAX Clock High Maximum Cycles 24 8 read-write TLOWM Master Clock Stretch Maximum Cycles 16 8 read-write TLOWS Slave Clock Stretch Maximum Cycles 8 8 read-write SMR Slave Mode Register 0x8 32 read-write n 0x0 0x0 MASK Slave Address Mask 8 7 read-write NACKEN Slave Receiver Data Phase NACK enable 0 1 read-write SADR Slave Address 16 7 read-write SCLWSDIS Clock Wait State Disable 6 1 read-write SMDA SMBus Default Address 2 1 read-write SMHH SMBus Host Header 3 1 read-write SR Status Register 0x20 32 read-only n 0x0 0x0 ARBLST Arbitration Lost (clear on read) 9 1 read-only ENDRX End of RX Buffer 12 1 read-only ENDTX End of TX Buffer 13 1 read-only EOSACC End Of Slave Access (clear on read) 11 1 read-only GACC General Call Access (clear on read) 5 1 read-only MCACK Master Code Acknowledge 16 1 read-only NACK Not Acknowledged (clear on read) 8 1 read-only OVRE Overrun Error (clear on read) 6 1 read-only PECERR PEC Error 19 1 read-only RXBUFF RX Buffer Full 14 1 read-only RXRDY Receive Holding Register Ready (automatically set / reset) 1 1 read-only SCL SCL line value 24 1 read-only SCLWS Clock Wait State (automatically set / reset) 10 1 read-only SDA SDA line value 25 1 read-only SMBDAM SMBus Default Address Match 20 1 read-only SMBHHM SMBus Host Header Address Match 21 1 read-only SVACC Slave Access (automatically set / reset) 4 1 read-only SVREAD Slave Read (automatically set / reset) 3 1 read-only TOUT Timeout Error 18 1 read-only TXBUFE TX Buffer Empty 15 1 read-only TXCOMP Transmission Completed (automatically set / reset) 0 1 read-only TXRDY Transmit Holding Register Ready (automatically set / reset) 2 1 read-only UNRE Underrun Error (clear on read) 7 1 read-only TCR Transmit Counter Register 0x10C 32 read-write n 0x0 0x0 TXCTR Transmit Counter Register 0 16 read-write THR Transmit Holding Register 0x34 32 write-only n 0x0 0x0 TXDATA Master or Slave Transmit Holding Data 0 8 write-only TNCR Transmit Next Counter Register 0x11C 32 read-write n 0x0 0x0 TXNCTR Transmit Counter Next 0 16 read-write TNPR Transmit Next Pointer Register 0x118 32 read-write n 0x0 0x0 TXNPTR Transmit Next Pointer 0 32 read-write TPR Transmit Pointer Register 0x108 32 read-write n 0x0 0x0 TXPTR Transmit Counter Register 0 32 read-write WPMR Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 0x545749 WPSR Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protect Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 24 read-only TWI1 Two-wire Interface 1 TWI 0x0 0x0 0x50 registers n TWI1 20 CR Control Register 0x0 32 write-only n 0x0 0x0 MSDIS TWI Master Mode Disabled 3 1 write-only MSEN TWI Master Mode Enabled 2 1 write-only QUICK SMBUS Quick Command 6 1 write-only START Send a START Condition 0 1 write-only STOP Send a STOP Condition 1 1 write-only SVDIS TWI Slave Mode Disabled 5 1 write-only SVEN TWI Slave Mode Enabled 4 1 write-only SWRST Software Reset 7 1 write-only CWGR Clock Waveform Generator Register 0x10 32 read-write n 0x0 0x0 CHDIV Clock High Divider 8 8 read-write CKDIV Clock Divider 16 3 read-write CLDIV Clock Low Divider 0 8 read-write HOLD TWD Hold Time versus TWCK falling 24 5 read-write IADR Internal Address Register 0xC 32 read-write n 0x0 0x0 IADR Internal Address 0 24 read-write IDR Interrupt Disable Register 0x28 32 write-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Disable 9 1 write-only ENDRX End of Receive Buffer Interrupt Disable 12 1 write-only ENDTX End of Transmit Buffer Interrupt Disable 13 1 write-only EOSACC End Of Slave Access Interrupt Disable 11 1 write-only GACC General Call Access Interrupt Disable 5 1 write-only NACK Not Acknowledge Interrupt Disable 8 1 write-only OVRE Overrun Error Interrupt Disable 6 1 write-only RXBUFF Receive Buffer Full Interrupt Disable 14 1 write-only RXRDY Receive Holding Register Ready Interrupt Disable 1 1 write-only SCL_WS Clock Wait State Interrupt Disable 10 1 write-only SVACC Slave Access Interrupt Disable 4 1 write-only TXBUFE Transmit Buffer Empty Interrupt Disable 15 1 write-only TXCOMP Transmission Completed Interrupt Disable 0 1 write-only TXRDY Transmit Holding Register Ready Interrupt Disable 2 1 write-only IER Interrupt Enable Register 0x24 32 write-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Enable 9 1 write-only ENDRX End of Receive Buffer Interrupt Enable 12 1 write-only ENDTX End of Transmit Buffer Interrupt Enable 13 1 write-only EOSACC End Of Slave Access Interrupt Enable 11 1 write-only GACC General Call Access Interrupt Enable 5 1 write-only NACK Not Acknowledge Interrupt Enable 8 1 write-only OVRE Overrun Error Interrupt Enable 6 1 write-only RXBUFF Receive Buffer Full Interrupt Enable 14 1 write-only RXRDY Receive Holding Register Ready Interrupt Enable 1 1 write-only SCL_WS Clock Wait State Interrupt Enable 10 1 write-only SVACC Slave Access Interrupt Enable 4 1 write-only TXBUFE Transmit Buffer Empty Interrupt Enable 15 1 write-only TXCOMP Transmission Completed Interrupt Enable 0 1 write-only TXRDY Transmit Holding Register Ready Interrupt Enable 2 1 write-only IMR Interrupt Mask Register 0x2C 32 read-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Mask 9 1 read-only ENDRX End of Receive Buffer Interrupt Mask 12 1 read-only ENDTX End of Transmit Buffer Interrupt Mask 13 1 read-only EOSACC End Of Slave Access Interrupt Mask 11 1 read-only GACC General Call Access Interrupt Mask 5 1 read-only NACK Not Acknowledge Interrupt Mask 8 1 read-only OVRE Overrun Error Interrupt Mask 6 1 read-only RXBUFF Receive Buffer Full Interrupt Mask 14 1 read-only RXRDY Receive Holding Register Ready Interrupt Mask 1 1 read-only SCL_WS Clock Wait State Interrupt Mask 10 1 read-only SVACC Slave Access Interrupt Mask 4 1 read-only TXBUFE Transmit Buffer Empty Interrupt Mask 15 1 read-only TXCOMP Transmission Completed Interrupt Mask 0 1 read-only TXRDY Transmit Holding Register Ready Interrupt Mask 2 1 read-only MMR Master Mode Register 0x4 32 read-write n 0x0 0x0 DADR Device Address 16 7 read-write IADRSZ Internal Device Address Size 8 2 read-write NONE No internal device address 0x0 1_BYTE One-byte internal device address 0x1 2_BYTE Two-byte internal device address 0x2 3_BYTE Three-byte internal device address 0x3 MREAD Master Read Direction 12 1 read-write PTCR Transfer Control Register 0x120 32 write-only n 0x0 0x0 RXTDIS Receiver Transfer Disable 1 1 write-only RXTEN Receiver Transfer Enable 0 1 write-only TXTDIS Transmitter Transfer Disable 9 1 write-only TXTEN Transmitter Transfer Enable 8 1 write-only PTSR Transfer Status Register 0x124 32 read-only n 0x0 0x0 RXTEN Receiver Transfer Enable 0 1 read-only TXTEN Transmitter Transfer Enable 8 1 read-only RCR Receive Counter Register 0x104 32 read-write n 0x0 0x0 RXCTR Receive Counter Register 0 16 read-write RHR Receive Holding Register 0x30 32 read-only n 0x0 0x0 RXDATA Master or Slave Receive Holding Data 0 8 read-only RNCR Receive Next Counter Register 0x114 32 read-write n 0x0 0x0 RXNCTR Receive Next Counter 0 16 read-write RNPR Receive Next Pointer Register 0x110 32 read-write n 0x0 0x0 RXNPTR Receive Next Pointer 0 32 read-write RPR Receive Pointer Register 0x100 32 read-write n 0x0 0x0 RXPTR Receive Pointer Register 0 32 read-write SMR Slave Mode Register 0x8 32 read-write n 0x0 0x0 SADR Slave Address 16 7 read-write SR Status Register 0x20 32 read-only n 0x0 0x0 ARBLST Arbitration Lost (clear on read) 9 1 read-only ENDRX End of RX buffer 12 1 read-only ENDTX End of TX buffer 13 1 read-only EOSACC End Of Slave Access (clear on read) 11 1 read-only GACC General Call Access (clear on read) 5 1 read-only NACK Not Acknowledged (clear on read) 8 1 read-only OVRE Overrun Error (clear on read) 6 1 read-only RXBUFF RX Buffer Full 14 1 read-only RXRDY Receive Holding Register Ready (automatically set / reset) 1 1 read-only SCLWS Clock Wait State (automatically set / reset) 10 1 read-only SVACC Slave Access (automatically set / reset) 4 1 read-only SVREAD Slave Read (automatically set / reset) 3 1 read-only TXBUFE TX Buffer Empty 15 1 read-only TXCOMP Transmission Completed (automatically set / reset) 0 1 read-only TXRDY Transmit Holding Register Ready (automatically set / reset) 2 1 read-only TCR Transmit Counter Register 0x10C 32 read-write n 0x0 0x0 TXCTR Transmit Counter Register 0 16 read-write THR Transmit Holding Register 0x34 32 write-only n 0x0 0x0 TXDATA Master or Slave Transmit Holding Data 0 8 write-only TNCR Transmit Next Counter Register 0x11C 32 read-write n 0x0 0x0 TXNCTR Transmit Counter Next 0 16 read-write TNPR Transmit Next Pointer Register 0x118 32 read-write n 0x0 0x0 TXNPTR Transmit Next Pointer 0 32 read-write TPR Transmit Pointer Register 0x108 32 read-write n 0x0 0x0 TXPTR Transmit Counter Register 0 32 read-write WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 0x545749 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 24 read-only TWI2 Two-wire Interface 2 TWI 0x0 0x0 0x50 registers n TWI2 22 CR Control Register 0x0 32 write-only n 0x0 0x0 MSDIS TWI Master Mode Disabled 3 1 write-only MSEN TWI Master Mode Enabled 2 1 write-only QUICK SMBUS Quick Command 6 1 write-only START Send a START Condition 0 1 write-only STOP Send a STOP Condition 1 1 write-only SVDIS TWI Slave Mode Disabled 5 1 write-only SVEN TWI Slave Mode Enabled 4 1 write-only SWRST Software Reset 7 1 write-only CWGR Clock Waveform Generator Register 0x10 32 read-write n 0x0 0x0 CHDIV Clock High Divider 8 8 read-write CKDIV Clock Divider 16 3 read-write CLDIV Clock Low Divider 0 8 read-write HOLD TWD Hold Time versus TWCK falling 24 5 read-write IADR Internal Address Register 0xC 32 read-write n 0x0 0x0 IADR Internal Address 0 24 read-write IDR Interrupt Disable Register 0x28 32 write-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Disable 9 1 write-only ENDRX End of Receive Buffer Interrupt Disable 12 1 write-only ENDTX End of Transmit Buffer Interrupt Disable 13 1 write-only EOSACC End Of Slave Access Interrupt Disable 11 1 write-only GACC General Call Access Interrupt Disable 5 1 write-only NACK Not Acknowledge Interrupt Disable 8 1 write-only OVRE Overrun Error Interrupt Disable 6 1 write-only RXBUFF Receive Buffer Full Interrupt Disable 14 1 write-only RXRDY Receive Holding Register Ready Interrupt Disable 1 1 write-only SCL_WS Clock Wait State Interrupt Disable 10 1 write-only SVACC Slave Access Interrupt Disable 4 1 write-only TXBUFE Transmit Buffer Empty Interrupt Disable 15 1 write-only TXCOMP Transmission Completed Interrupt Disable 0 1 write-only TXRDY Transmit Holding Register Ready Interrupt Disable 2 1 write-only IER Interrupt Enable Register 0x24 32 write-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Enable 9 1 write-only ENDRX End of Receive Buffer Interrupt Enable 12 1 write-only ENDTX End of Transmit Buffer Interrupt Enable 13 1 write-only EOSACC End Of Slave Access Interrupt Enable 11 1 write-only GACC General Call Access Interrupt Enable 5 1 write-only NACK Not Acknowledge Interrupt Enable 8 1 write-only OVRE Overrun Error Interrupt Enable 6 1 write-only RXBUFF Receive Buffer Full Interrupt Enable 14 1 write-only RXRDY Receive Holding Register Ready Interrupt Enable 1 1 write-only SCL_WS Clock Wait State Interrupt Enable 10 1 write-only SVACC Slave Access Interrupt Enable 4 1 write-only TXBUFE Transmit Buffer Empty Interrupt Enable 15 1 write-only TXCOMP Transmission Completed Interrupt Enable 0 1 write-only TXRDY Transmit Holding Register Ready Interrupt Enable 2 1 write-only IMR Interrupt Mask Register 0x2C 32 read-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Mask 9 1 read-only ENDRX End of Receive Buffer Interrupt Mask 12 1 read-only ENDTX End of Transmit Buffer Interrupt Mask 13 1 read-only EOSACC End Of Slave Access Interrupt Mask 11 1 read-only GACC General Call Access Interrupt Mask 5 1 read-only NACK Not Acknowledge Interrupt Mask 8 1 read-only OVRE Overrun Error Interrupt Mask 6 1 read-only RXBUFF Receive Buffer Full Interrupt Mask 14 1 read-only RXRDY Receive Holding Register Ready Interrupt Mask 1 1 read-only SCL_WS Clock Wait State Interrupt Mask 10 1 read-only SVACC Slave Access Interrupt Mask 4 1 read-only TXBUFE Transmit Buffer Empty Interrupt Mask 15 1 read-only TXCOMP Transmission Completed Interrupt Mask 0 1 read-only TXRDY Transmit Holding Register Ready Interrupt Mask 2 1 read-only MMR Master Mode Register 0x4 32 read-write n 0x0 0x0 DADR Device Address 16 7 read-write IADRSZ Internal Device Address Size 8 2 read-write NONE No internal device address 0x0 1_BYTE One-byte internal device address 0x1 2_BYTE Two-byte internal device address 0x2 3_BYTE Three-byte internal device address 0x3 MREAD Master Read Direction 12 1 read-write PTCR Transfer Control Register 0x120 32 write-only n 0x0 0x0 RXTDIS Receiver Transfer Disable 1 1 write-only RXTEN Receiver Transfer Enable 0 1 write-only TXTDIS Transmitter Transfer Disable 9 1 write-only TXTEN Transmitter Transfer Enable 8 1 write-only PTSR Transfer Status Register 0x124 32 read-only n 0x0 0x0 RXTEN Receiver Transfer Enable 0 1 read-only TXTEN Transmitter Transfer Enable 8 1 read-only RCR Receive Counter Register 0x104 32 read-write n 0x0 0x0 RXCTR Receive Counter Register 0 16 read-write RHR Receive Holding Register 0x30 32 read-only n 0x0 0x0 RXDATA Master or Slave Receive Holding Data 0 8 read-only RNCR Receive Next Counter Register 0x114 32 read-write n 0x0 0x0 RXNCTR Receive Next Counter 0 16 read-write RNPR Receive Next Pointer Register 0x110 32 read-write n 0x0 0x0 RXNPTR Receive Next Pointer 0 32 read-write RPR Receive Pointer Register 0x100 32 read-write n 0x0 0x0 RXPTR Receive Pointer Register 0 32 read-write SMR Slave Mode Register 0x8 32 read-write n 0x0 0x0 SADR Slave Address 16 7 read-write SR Status Register 0x20 32 read-only n 0x0 0x0 ARBLST Arbitration Lost (clear on read) 9 1 read-only ENDRX End of RX buffer 12 1 read-only ENDTX End of TX buffer 13 1 read-only EOSACC End Of Slave Access (clear on read) 11 1 read-only GACC General Call Access (clear on read) 5 1 read-only NACK Not Acknowledged (clear on read) 8 1 read-only OVRE Overrun Error (clear on read) 6 1 read-only RXBUFF RX Buffer Full 14 1 read-only RXRDY Receive Holding Register Ready (automatically set / reset) 1 1 read-only SCLWS Clock Wait State (automatically set / reset) 10 1 read-only SVACC Slave Access (automatically set / reset) 4 1 read-only SVREAD Slave Read (automatically set / reset) 3 1 read-only TXBUFE TX Buffer Empty 15 1 read-only TXCOMP Transmission Completed (automatically set / reset) 0 1 read-only TXRDY Transmit Holding Register Ready (automatically set / reset) 2 1 read-only TCR Transmit Counter Register 0x10C 32 read-write n 0x0 0x0 TXCTR Transmit Counter Register 0 16 read-write THR Transmit Holding Register 0x34 32 write-only n 0x0 0x0 TXDATA Master or Slave Transmit Holding Data 0 8 write-only TNCR Transmit Next Counter Register 0x11C 32 read-write n 0x0 0x0 TXNCTR Transmit Counter Next 0 16 read-write TNPR Transmit Next Pointer Register 0x118 32 read-write n 0x0 0x0 TXNPTR Transmit Next Pointer 0 32 read-write TPR Transmit Pointer Register 0x108 32 read-write n 0x0 0x0 TXPTR Transmit Counter Register 0 32 read-write WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 0x545749 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 24 read-only UART0 Universal Asynchronous Receiver Transmitter 0 UART 0x0 0x0 0x128 registers n UART0 8 BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 0x0 CD Clock Divisor 0 16 read-write CR Control Register 0x0 32 write-only n 0x0 0x0 RSTRX Reset Receiver 2 1 write-only RSTSTA Reset Status Bits 8 1 write-only RSTTX Reset Transmitter 3 1 write-only RXDIS Receiver Disable 5 1 write-only RXEN Receiver Enable 4 1 write-only TXDIS Transmitter Disable 7 1 write-only TXEN Transmitter Enable 6 1 write-only IDR Interrupt Disable Register 0xC 32 write-only n 0x0 0x0 ENDRX Disable End of Receive Transfer Interrupt 3 1 write-only ENDTX Disable End of Transmit Interrupt 4 1 write-only FRAME Disable Framing Error Interrupt 6 1 write-only OVRE Disable Overrun Error Interrupt 5 1 write-only PARE Disable Parity Error Interrupt 7 1 write-only RXBUFF Disable Buffer Full Interrupt 12 1 write-only RXRDY Disable RXRDY Interrupt 0 1 write-only TXBUFE Disable Buffer Empty Interrupt 11 1 write-only TXEMPTY Disable TXEMPTY Interrupt 9 1 write-only TXRDY Disable TXRDY Interrupt 1 1 write-only IER Interrupt Enable Register 0x8 32 write-only n 0x0 0x0 ENDRX Enable End of Receive Transfer Interrupt 3 1 write-only ENDTX Enable End of Transmit Interrupt 4 1 write-only FRAME Enable Framing Error Interrupt 6 1 write-only OVRE Enable Overrun Error Interrupt 5 1 write-only PARE Enable Parity Error Interrupt 7 1 write-only RXBUFF Enable Buffer Full Interrupt 12 1 write-only RXRDY Enable RXRDY Interrupt 0 1 write-only TXBUFE Enable Buffer Empty Interrupt 11 1 write-only TXEMPTY Enable TXEMPTY Interrupt 9 1 write-only TXRDY Enable TXRDY Interrupt 1 1 write-only IMR Interrupt Mask Register 0x10 32 read-only n 0x0 0x0 ENDRX Mask End of Receive Transfer Interrupt 3 1 read-only ENDTX Mask End of Transmit Interrupt 4 1 read-only FRAME Mask Framing Error Interrupt 6 1 read-only OVRE Mask Overrun Error Interrupt 5 1 read-only PARE Mask Parity Error Interrupt 7 1 read-only RXBUFF Mask RXBUFF Interrupt 12 1 read-only RXRDY Mask RXRDY Interrupt 0 1 read-only TXBUFE Mask TXBUFE Interrupt 11 1 read-only TXEMPTY Mask TXEMPTY Interrupt 9 1 read-only TXRDY Disable TXRDY Interrupt 1 1 read-only MR Mode Register 0x4 32 read-write n 0x0 0x0 CHMODE Channel Mode 14 2 read-write NORMAL Normal mode 0x0 AUTOMATIC Automatic echo 0x1 LOCAL_LOOPBACK Local loopback 0x2 REMOTE_LOOPBACK Remote loopback 0x3 FILTER Receiver Digital Filter 4 1 read-write DISABLED UART does not filter the receive line. 0 ENABLED UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). 1 PAR Parity Type 9 3 read-write EVEN Even Parity 0x0 ODD Odd Parity 0x1 SPACE Space: parity forced to 0 0x2 MARK Mark: parity forced to 1 0x3 NO No parity 0x4 PTCR Transfer Control Register 0x120 32 write-only n 0x0 0x0 RXTDIS Receiver Transfer Disable 1 1 write-only RXTEN Receiver Transfer Enable 0 1 write-only TXTDIS Transmitter Transfer Disable 9 1 write-only TXTEN Transmitter Transfer Enable 8 1 write-only PTSR Transfer Status Register 0x124 32 read-only n 0x0 0x0 RXTEN Receiver Transfer Enable 0 1 read-only TXTEN Transmitter Transfer Enable 8 1 read-only RCR Receive Counter Register 0x104 32 read-write n 0x0 0x0 RXCTR Receive Counter Register 0 16 read-write RHR Receive Holding Register 0x18 32 read-only n 0x0 0x0 RXCHR Received Character 0 8 read-only RNCR Receive Next Counter Register 0x114 32 read-write n 0x0 0x0 RXNCTR Receive Next Counter 0 16 read-write RNPR Receive Next Pointer Register 0x110 32 read-write n 0x0 0x0 RXNPTR Receive Next Pointer 0 32 read-write RPR Receive Pointer Register 0x100 32 read-write n 0x0 0x0 RXPTR Receive Pointer Register 0 32 read-write SR Status Register 0x14 32 read-only n 0x0 0x0 ENDRX End of Receiver Transfer 3 1 read-only ENDTX End of Transmitter Transfer 4 1 read-only FRAME Framing Error 6 1 read-only OVRE Overrun Error 5 1 read-only PARE Parity Error 7 1 read-only RXBUFF Receive Buffer Full 12 1 read-only RXRDY Receiver Ready 0 1 read-only TXBUFE Transmission Buffer Empty 11 1 read-only TXEMPTY Transmitter Empty 9 1 read-only TXRDY Transmitter Ready 1 1 read-only TCR Transmit Counter Register 0x10C 32 read-write n 0x0 0x0 TXCTR Transmit Counter Register 0 16 read-write THR Transmit Holding Register 0x1C 32 write-only n 0x0 0x0 TXCHR Character to be Transmitted 0 8 write-only TNCR Transmit Next Counter Register 0x11C 32 read-write n 0x0 0x0 TXNCTR Transmit Counter Next 0 16 read-write TNPR Transmit Next Pointer Register 0x118 32 read-write n 0x0 0x0 TXNPTR Transmit Next Pointer 0 32 read-write TPR Transmit Pointer Register 0x108 32 read-write n 0x0 0x0 TXPTR Transmit Counter Register 0 32 read-write UART1 Universal Asynchronous Receiver Transmitter 1 UART 0x0 0x0 0x128 registers n UART1 9 BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 0x0 CD Clock Divisor 0 16 read-write CR Control Register 0x0 32 write-only n 0x0 0x0 RSTRX Reset Receiver 2 1 write-only RSTSTA Reset Status Bits 8 1 write-only RSTTX Reset Transmitter 3 1 write-only RXDIS Receiver Disable 5 1 write-only RXEN Receiver Enable 4 1 write-only TXDIS Transmitter Disable 7 1 write-only TXEN Transmitter Enable 6 1 write-only IDR Interrupt Disable Register 0xC 32 write-only n 0x0 0x0 ENDRX Disable End of Receive Transfer Interrupt 3 1 write-only ENDTX Disable End of Transmit Interrupt 4 1 write-only FRAME Disable Framing Error Interrupt 6 1 write-only OVRE Disable Overrun Error Interrupt 5 1 write-only PARE Disable Parity Error Interrupt 7 1 write-only RXBUFF Disable Buffer Full Interrupt 12 1 write-only RXRDY Disable RXRDY Interrupt 0 1 write-only TXBUFE Disable Buffer Empty Interrupt 11 1 write-only TXEMPTY Disable TXEMPTY Interrupt 9 1 write-only TXRDY Disable TXRDY Interrupt 1 1 write-only IER Interrupt Enable Register 0x8 32 write-only n 0x0 0x0 ENDRX Enable End of Receive Transfer Interrupt 3 1 write-only ENDTX Enable End of Transmit Interrupt 4 1 write-only FRAME Enable Framing Error Interrupt 6 1 write-only OVRE Enable Overrun Error Interrupt 5 1 write-only PARE Enable Parity Error Interrupt 7 1 write-only RXBUFF Enable Buffer Full Interrupt 12 1 write-only RXRDY Enable RXRDY Interrupt 0 1 write-only TXBUFE Enable Buffer Empty Interrupt 11 1 write-only TXEMPTY Enable TXEMPTY Interrupt 9 1 write-only TXRDY Enable TXRDY Interrupt 1 1 write-only IMR Interrupt Mask Register 0x10 32 read-only n 0x0 0x0 ENDRX Mask End of Receive Transfer Interrupt 3 1 read-only ENDTX Mask End of Transmit Interrupt 4 1 read-only FRAME Mask Framing Error Interrupt 6 1 read-only OVRE Mask Overrun Error Interrupt 5 1 read-only PARE Mask Parity Error Interrupt 7 1 read-only RXBUFF Mask RXBUFF Interrupt 12 1 read-only RXRDY Mask RXRDY Interrupt 0 1 read-only TXBUFE Mask TXBUFE Interrupt 11 1 read-only TXEMPTY Mask TXEMPTY Interrupt 9 1 read-only TXRDY Disable TXRDY Interrupt 1 1 read-only MR Mode Register 0x4 32 read-write n 0x0 0x0 CHMODE Channel Mode 14 2 read-write NORMAL Normal mode 0x0 AUTOMATIC Automatic echo 0x1 LOCAL_LOOPBACK Local loopback 0x2 REMOTE_LOOPBACK Remote loopback 0x3 FILTER Receiver Digital Filter 4 1 read-write DISABLED UART does not filter the receive line. 0 ENABLED UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). 1 PAR Parity Type 9 3 read-write EVEN Even Parity 0x0 ODD Odd Parity 0x1 SPACE Space: parity forced to 0 0x2 MARK Mark: parity forced to 1 0x3 NO No parity 0x4 PTCR Transfer Control Register 0x120 32 write-only n 0x0 0x0 RXTDIS Receiver Transfer Disable 1 1 write-only RXTEN Receiver Transfer Enable 0 1 write-only TXTDIS Transmitter Transfer Disable 9 1 write-only TXTEN Transmitter Transfer Enable 8 1 write-only PTSR Transfer Status Register 0x124 32 read-only n 0x0 0x0 RXTEN Receiver Transfer Enable 0 1 read-only TXTEN Transmitter Transfer Enable 8 1 read-only RCR Receive Counter Register 0x104 32 read-write n 0x0 0x0 RXCTR Receive Counter Register 0 16 read-write RHR Receive Holding Register 0x18 32 read-only n 0x0 0x0 RXCHR Received Character 0 8 read-only RNCR Receive Next Counter Register 0x114 32 read-write n 0x0 0x0 RXNCTR Receive Next Counter 0 16 read-write RNPR Receive Next Pointer Register 0x110 32 read-write n 0x0 0x0 RXNPTR Receive Next Pointer 0 32 read-write RPR Receive Pointer Register 0x100 32 read-write n 0x0 0x0 RXPTR Receive Pointer Register 0 32 read-write SR Status Register 0x14 32 read-only n 0x0 0x0 ENDRX End of Receiver Transfer 3 1 read-only ENDTX End of Transmitter Transfer 4 1 read-only FRAME Framing Error 6 1 read-only OVRE Overrun Error 5 1 read-only PARE Parity Error 7 1 read-only RXBUFF Receive Buffer Full 12 1 read-only RXRDY Receiver Ready 0 1 read-only TXBUFE Transmission Buffer Empty 11 1 read-only TXEMPTY Transmitter Empty 9 1 read-only TXRDY Transmitter Ready 1 1 read-only TCR Transmit Counter Register 0x10C 32 read-write n 0x0 0x0 TXCTR Transmit Counter Register 0 16 read-write THR Transmit Holding Register 0x1C 32 write-only n 0x0 0x0 TXCHR Character to be Transmitted 0 8 write-only TNCR Transmit Next Counter Register 0x11C 32 read-write n 0x0 0x0 TXNCTR Transmit Counter Next 0 16 read-write TNPR Transmit Next Pointer Register 0x118 32 read-write n 0x0 0x0 TXNPTR Transmit Next Pointer 0 32 read-write TPR Transmit Pointer Register 0x108 32 read-write n 0x0 0x0 TXPTR Transmit Counter Register 0 32 read-write USART Universal Synchronous Asynchronous Receiver Transmitter USART 0x0 0x0 0x50 registers n USART 14 BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 0x0 CD Clock Divider 0 16 read-write FP Fractional Part 16 3 read-write CR Control Register 0x0 32 write-only n 0x0 0x0 RETTO Rearm Time-out 15 1 write-only RSTIT Reset Iterations 13 1 write-only RSTNACK Reset Non Acknowledge 14 1 write-only RSTRX Reset Receiver 2 1 write-only RSTSTA Reset Status Bits 8 1 write-only RSTTX Reset Transmitter 3 1 write-only RTSDIS Request to Send Disable 19 1 write-only RTSEN Request to Send Enable 18 1 write-only RXDIS Receiver Disable 5 1 write-only RXEN Receiver Enable 4 1 write-only SENDA Send Address 12 1 write-only STPBRK Stop Break 10 1 write-only STTBRK Start Break 9 1 write-only STTTO Start Time-out 11 1 write-only TXDIS Transmitter Disable 7 1 write-only TXEN Transmitter Enable 6 1 write-only CR_SPI_MODE Control Register SPI_MODE 0x0 32 write-only n 0x0 0x0 FCS Force SPI Chip Select 18 1 write-only RCS Release SPI Chip Select 19 1 write-only RSTRX Reset Receiver 2 1 write-only RSTSTA Reset Status Bits 8 1 write-only RSTTX Reset Transmitter 3 1 write-only RXDIS Receiver Disable 5 1 write-only RXEN Receiver Enable 4 1 write-only TXDIS Transmitter Disable 7 1 write-only TXEN Transmitter Enable 6 1 write-only CSR Channel Status Register 0x14 32 read-only n 0x0 0x0 CTS Image of CTS Input 23 1 read-only CTSIC Clear to Send Input Change Flag 19 1 read-only ENDRX End of Receiver Transfer 3 1 read-only ENDTX End of Transmitter Transfer 4 1 read-only FRAME Framing Error 6 1 read-only ITER Max Number of Repetitions Reached 10 1 read-only NACK Non AcknowledgeInterrupt 13 1 read-only OVRE Overrun Error 5 1 read-only PARE Parity Error 7 1 read-only RXBRK Break Received/End of Break 2 1 read-only RXBUFF Reception Buffer Full 12 1 read-only RXRDY Receiver Ready 0 1 read-only TIMEOUT Receiver Time-out 8 1 read-only TXBUFE Transmission Buffer Empty 11 1 read-only TXEMPTY Transmitter Empty 9 1 read-only TXRDY Transmitter Ready 1 1 read-only CSR_SPI_MODE Channel Status Register SPI_MODE 0x14 32 read-only n 0x0 0x0 ENDRX 3 1 read-only ENDTX 4 1 read-only OVRE Overrun Error 5 1 read-only RXBUFF 12 1 read-only RXRDY Receiver Ready 0 1 read-only TXBUFE 11 1 read-only TXEMPTY Transmitter Empty 9 1 read-only TXRDY Transmitter Ready 1 1 read-only UNRE Underrun Error 10 1 read-only FIDI FI DI Ratio Register 0x40 32 read-write n 0x0 0x0 FI_DI_RATIO FI Over DI Ratio Value 0 11 read-write IDR Interrupt Disable Register 0xC 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Disable 19 1 write-only ENDRX End of Receive Transfer Interrupt Disable (available in all USART modes of operation) 3 1 write-only ENDTX End of Transmit Interrupt Disable (available in all USART modes of operation) 4 1 write-only FRAME Framing Error Interrupt Disable 6 1 write-only ITER Max Number of Repetitions Reached Interrupt Disable 10 1 write-only NACK Non AcknowledgeInterrupt Disable 13 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only PARE Parity Error Interrupt Disable 7 1 write-only RXBRK Receiver Break Interrupt Disable 2 1 write-only RXBUFF Buffer Full Interrupt Disable (available in all USART modes of operation) 12 1 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TIMEOUT Time-out Interrupt Disable 8 1 write-only TXBUFE Buffer Empty Interrupt Disable (available in all USART modes of operation) 11 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only IDR_SPI_MODE Interrupt Disable Register SPI_MODE 0xC 32 write-only n 0x0 0x0 ENDRX 3 1 write-only ENDTX 4 1 write-only OVRE Overrun Error Interrupt Disable 5 1 write-only RXBUFF 12 1 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TXBUFE 11 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only UNRE SPI Underrun Error Interrupt Disable 10 1 write-only IER Interrupt Enable Register 0x8 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Enable 19 1 write-only ENDRX End of Receive Transfer Interrupt Enable (available in all USART modes of operation) 3 1 write-only ENDTX End of Transmit Interrupt Enable (available in all USART modes of operation) 4 1 write-only FRAME Framing Error Interrupt Enable 6 1 write-only ITER Max number of Repetitions Reached Interrupt Enable 10 1 write-only NACK Non AcknowledgeInterrupt Enable 13 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only PARE Parity Error Interrupt Enable 7 1 write-only RXBRK Receiver Break Interrupt Enable 2 1 write-only RXBUFF Buffer Full Interrupt Enable (available in all USART modes of operation) 12 1 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TIMEOUT Time-out Interrupt Enable 8 1 write-only TXBUFE Buffer Empty Interrupt Enable (available in all USART modes of operation) 11 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only IER_SPI_MODE Interrupt Enable Register SPI_MODE 0x8 32 write-only n 0x0 0x0 ENDRX 3 1 write-only ENDTX 4 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only RXBUFF 12 1 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TXBUFE 11 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only UNRE SPI Underrun Error Interrupt Enable 10 1 write-only IF IrDA Filter Register 0x4C 32 read-write n 0x0 0x0 IRDA_FILTER IrDA Filter 0 8 read-write IMR Interrupt Mask Register 0x10 32 read-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Mask 19 1 read-only ENDRX End of Receive Transfer Interrupt Mask (available in all USART modes of operation) 3 1 read-only ENDTX End of Transmit Interrupt Mask (available in all USART modes of operation) 4 1 read-only FRAME Framing Error Interrupt Mask 6 1 read-only ITER Max Number of Repetitions Reached Interrupt Mask 10 1 read-only NACK Non AcknowledgeInterrupt Mask 13 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only PARE Parity Error Interrupt Mask 7 1 read-only RXBRK Receiver Break Interrupt Mask 2 1 read-only RXBUFF Buffer Full Interrupt Mask (available in all USART modes of operation) 12 1 read-only RXRDY RXRDY Interrupt Mask 0 1 read-only TIMEOUT Time-out Interrupt Mask 8 1 read-only TXBUFE Buffer Empty Interrupt Mask (available in all USART modes of operation) 11 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only IMR_SPI_MODE Interrupt Mask Register SPI_MODE 0x10 32 read-only n 0x0 0x0 ENDRX 3 1 read-only ENDTX 4 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only RXBUFF 12 1 read-only RXRDY RXRDY Interrupt Mask 0 1 read-only TXBUFE 11 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only UNRE SPI Underrun Error Interrupt Mask 10 1 read-only MR Mode Register 0x4 32 read-write n 0x0 0x0 CHMODE Channel Mode 14 2 read-write NORMAL Normal mode 0x0 AUTOMATIC Automatic Echo. Receiver input is connected to the TXD pin. 0x1 LOCAL_LOOPBACK Local Loopback. Transmitter output is connected to the Receiver Input. 0x2 REMOTE_LOOPBACK Remote Loopback. RXD pin is internally connected to the TXD pin. 0x3 CHRL Character Length 6 2 read-write 5_BIT Character length is 5 bits 0x0 6_BIT Character length is 6 bits 0x1 7_BIT Character length is 7 bits 0x2 8_BIT Character length is 8 bits 0x3 CLKO Clock Output Select 18 1 read-write DSNACK Disable Successive NACK 21 1 read-write FILTER Infrared Receive Line Filter 28 1 read-write INACK Inhibit Non Acknowledge 20 1 read-write INVDATA Inverted Data 23 1 read-write MAX_ITERATION Maximum Number of Automatic Iteration 24 3 read-write MODE9 9-bit Character Length 17 1 read-write MSBF Bit Order 16 1 read-write NBSTOP Number of Stop Bits 12 2 read-write 1_BIT 1 stop bit 0x0 1_5_BIT 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) 0x1 2_BIT 2 stop bits 0x2 OVER Oversampling Mode 19 1 read-write PAR Parity Type 9 3 read-write EVEN Even parity 0x0 ODD Odd parity 0x1 SPACE Parity forced to 0 (Space) 0x2 MARK Parity forced to 1 (Mark) 0x3 NO No parity 0x4 MULTIDROP Multidrop mode 0x6 SYNC Synchronous Mode Select 8 1 read-write USART_MODE USART Mode of Operation 0 4 read-write NORMAL Normal mode 0x0 RS485 RS485 0x1 HW_HANDSHAKING Hardware Handshaking 0x2 IS07816_T_0 IS07816 Protocol: T = 0 0x4 IS07816_T_1 IS07816 Protocol: T = 1 0x6 IRDA IrDA 0x8 SPI_MASTER SPI master 0xE SPI_SLAVE SPI Slave 0xF USCLKS Clock Selection 4 2 read-write MCK master Clock MCK is selected 0x0 DIV Internal Clock Divided MCK/DIV (DIV=8) is selected 0x1 SCK Serial Clock SLK is selected 0x3 MR_SPI_MODE Mode Register SPI_MODE 0x4 32 read-write n 0x0 0x0 CHRL Character Length 6 2 read-write 8_BIT Character length is 8 bits 0x3 CPHA SPI Clock Phase 8 1 read-write CPOL SPI Clock Polarity 16 1 read-write USART_MODE USART Mode of Operation 0 4 read-write SPI_MASTER SPI master 0xE SPI_SLAVE SPI Slave 0xF USCLKS Clock Selection 4 2 read-write MCK master Clock MCK is selected 0x0 DIV Internal Clock Divided MCK/DIV (DIV=8) is selected 0x1 SCK Serial Clock SLK is selected 0x3 WRDBT Wait Read Data Before Transfer 20 1 read-write NER Number of Errors Register 0x44 32 read-only n 0x0 0x0 NB_ERRORS Number of Errors 0 8 read-only PTCR Transfer Control Register 0x120 32 write-only n 0x0 0x0 RXTDIS Receiver Transfer Disable 1 1 write-only RXTEN Receiver Transfer Enable 0 1 write-only TXTDIS Transmitter Transfer Disable 9 1 write-only TXTEN Transmitter Transfer Enable 8 1 write-only PTSR Transfer Status Register 0x124 32 read-only n 0x0 0x0 RXTEN Receiver Transfer Enable 0 1 read-only TXTEN Transmitter Transfer Enable 8 1 read-only RCR Receive Counter Register 0x104 32 read-write n 0x0 0x0 RXCTR Receive Counter Register 0 16 read-write RHR Receive Holding Register 0x18 32 read-only n 0x0 0x0 RXCHR Received Character 0 9 read-only RXSYNH Received Sync 15 1 read-only RNCR Receive Next Counter Register 0x114 32 read-write n 0x0 0x0 RXNCTR Receive Next Counter 0 16 read-write RNPR Receive Next Pointer Register 0x110 32 read-write n 0x0 0x0 RXNPTR Receive Next Pointer 0 32 read-write RPR Receive Pointer Register 0x100 32 read-write n 0x0 0x0 RXPTR Receive Pointer Register 0 32 read-write RTOR Receiver Time-out Register 0x24 32 read-write n 0x0 0x0 TO Time-out Value 0 16 read-write TCR Transmit Counter Register 0x10C 32 read-write n 0x0 0x0 TXCTR Transmit Counter Register 0 16 read-write THR Transmit Holding Register 0x1C 32 write-only n 0x0 0x0 TXCHR Character to be Transmitted 0 9 write-only TXSYNH Sync Field to be Transmitted 15 1 write-only TNCR Transmit Next Counter Register 0x11C 32 read-write n 0x0 0x0 TXNCTR Transmit Counter Next 0 16 read-write TNPR Transmit Next Pointer Register 0x118 32 read-write n 0x0 0x0 TXNPTR Transmit Next Pointer 0 32 read-write TPR Transmit Pointer Register 0x108 32 read-write n 0x0 0x0 TXPTR Transmit Counter Register 0 32 read-write TTGR Transmitter Timeguard Register 0x28 32 read-write n 0x0 0x0 TG Timeguard Value 0 8 read-write WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 0x555341 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only WDT Watchdog Timer SYSC 0x0 0x0 0x200 registers n CR Control Register 0x0 32 write-only n 0x0 0x0 KEY Password. 24 8 write-only PASSWD Writing any other value in this field aborts the write operation. 0xA5 WDRSTT Watchdog Restart 0 1 write-only MR Mode Register 0x4 32 read-write n 0x0 0x0 WDD Watchdog Delta Value 16 12 read-write WDDBGHLT Watchdog Debug Halt 28 1 read-write WDDIS Watchdog Disable 15 1 read-write WDFIEN Watchdog Fault Interrupt Enable 12 1 read-write WDIDLEHLT Watchdog Idle Halt 29 1 read-write WDRPROC Watchdog Reset Processor 14 1 read-write WDRSTEN Watchdog Reset Enable 13 1 read-write WDV Watchdog Counter Value 0 12 read-write SR Status Register 0x8 32 read-only n 0x0 0x0 WDERR Watchdog Error 1 1 read-only WDUNF Watchdog Underflow 0 1 read-only